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OpenXiangShan / XiangShan

Open-source high-performance RISC-V processor
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L2TLB, RVH: change ppnlen from 24 to 29 for the first stage translation in two stage translation #3121

Closed pxk27 closed 2 days ago

pxk27 commented 4 days ago

The first stage is sv39 and the second stage is sv39x4. Before Xiangshan realizes H extension, the paddr is 36 bits, so ppnlen is 24 bits. After Xiangshan realizes H extension, the ppnlen of stage 1 should be 29 bits because the paddr of stage 1 is gpaddr for host and gpaddr is 41 bits. I add the gvpnlen to replace the ppnlen of stage 1 in L2TLB.

XiangShanRobot commented 4 days ago
[Generated by IPC robot] commit: f197a2a1e92ae56eb1a7a521b0579ad02cd308e8 commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
f197a2a 1.805 0.458 1.995 1.189 2.928 2.494 2.226 0.927 1.356 1.389 3.173 2.664 2.401 2.963
master branch: commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
195ef4a 0.458 1.995 1.189 2.224 0.927 1.356 1.389 3.173 2.664 2.963
6b46af8 1.804 0.458 1.995 1.189 2.928 2.494 2.224 0.927 1.378 1.389 3.173 2.664 2.401 2.963
b92f844 1.804 0.458 1.995 1.189 2.928 2.494 2.224 0.927 1.368 1.389 3.173 2.664 2.401 2.963
fe98272 0.451 2.036 1.184 2.196 0.935 1.381 3.183 2.666 2.961
344cf5d 1.828 0.451 2.036 1.184 2.938 2.497 2.196 0.935 1.381 1.280 3.183 2.666 2.403 2.961
c4a59f1 1.812 0.451 2.036 1.193 2.941 2.507 2.197 0.934 1.381 1.397 3.181 2.665 2.403 2.961
5110577 1.812 0.451 2.043 1.199 2.941 2.507 2.196 0.934 1.373 1.397 3.181 2.669 2.403 2.961
0d9b3da 1.812 0.451 2.043 1.199 2.941 2.507 2.196 0.934 1.373 1.397 3.181 2.669 2.403 2.961
842df08 1.812 0.451 2.043 1.199 2.941 2.507 2.196 0.934 1.373 1.397 3.181 2.669 2.403 2.961
03b2841 1.812 0.451 2.047 1.199 2.941 2.507 2.196 0.934 1.373 1.397 3.181 2.669 2.403 2.961