What is the stable version of Nanhu-V2 verified on FPGA?

xuyb1999 commented 2 months ago

Before start

[X] I have read the RISC-V ISA Manual and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册，这不是一个指令集相关的问题。
[X] I have read the XiangShan Documents. 我已经阅读过香山文档。
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Describe the question

您好，请问有在FPGA上验证通过的南湖V2的稳定版本吗？我看到release里面有两个v2.0和v2.1的tag，它们哪一个是通过FPGA验证，哪一个是流片的南湖V2版本呢？

Hello, may I ask if there is a stable version of Nanhu V2 that has been verified on FPGA? I noticed there are two tags, v2.0 and v2.1, in the release. Which one has been verified on FPGA, and which one is the taped-out version of Nanhu V2?

Tang-Haojin commented 2 months ago

The southlake branch or tag v2.1 is Nanhu V2. To place it on FPGA vu19p, you may referred to this patch.

xuyb1999 commented 1 month ago

我尝试将您提供的patch应用到tag v2.1对应的代码中，并处理了conflict，git diff如下： I have attempted to apply the patch you provided to the code corresponding to the tag v2.1, and resolved the conflicts. Here is the git diff:

diff --git a/src/main/scala/top/Configs.scala b/src/main/scala/top/Configs.scala
index c10650129..c769b6d3d 100644
--- a/src/main/scala/top/Configs.scala
+++ b/src/main/scala/top/Configs.scala
@@ -35,7 +35,7 @@ import huancun._

 class BaseConfig(n: Int) extends Config((site, here, up) => {
   case XLen => 64
-  case DebugOptionsKey => DebugOptions()
+  case DebugOptionsKey => DebugOptions(AlwaysBasicDiff=false)
   case SoCParamsKey => SoCParameters()
   case PMParameKey => PMParameters()
   case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) }
@@ -282,7 +282,7 @@ class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1
           address = 0x1f10040000L,
           numCores = tiles.size
         )),
-        sramClkDivBy2 = true,
+        sramClkDivBy2 = false,
         sramDepthDiv = 4,
         tagECC = Some("secded"),
         dataECC = Some("secded"),
@@ -311,15 +311,8 @@ class MediumConfig(n: Int = 1) extends Config(
 )

 class DefaultConfig(n: Int = 1) extends Config(
-  new WithNKBL3(2 * 1024, inclusive = false, banks = 4, ways = 8)
-    ++ new WithNKBL2(512, inclusive = false, banks = 4, alwaysReleaseData = true)
-    ++ new WithNKBL1D(128)
-    ++ new BaseConfig(n)
-)
-
-class FPGAConfig(n: Int = 1) extends Config(
-  new WithNKBL3(2 * 1024, inclusive = false, banks = 4, ways = 8)
-    ++ new WithNKBL2(512, inclusive = false, banks = 2, alwaysReleaseData = true)
-    ++ new WithNKBL1D(128)
+  new WithNKBL3(3 * 1024, inclusive = false, banks = 1, ways = 6)
+    ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4)
+    ++ new WithNKBL1D(64, ways = 4)
     ++ new BaseConfig(n)
 )

然而，我在执行make verilog命令时，出现了如下的错误导致编译无法通过，请问您知道是怎么回事吗？ However, when I executed the make verilog command, the following error occurred, causing the compilation to fail. Do you know what's going on?

        25 <= dma ID#24
        26 <= dma ID#25
        27 <= dma ID#26
        28 <= dma ID#27
        29 <= dma ID#28
        30 <= dma ID#29
        31 <= dma ID#30
        32 <= dma ID#31
        33 <= debug
Exception in thread "main" firrtl.passes.PassExceptions:
firrtl.passes.CheckInitialization$RefNotInitializedException:  : [module SinkC]  Reference io is not fully initialized.
   : io.taskack.bits.sink <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException:  : [module SinkC]  Reference io is not fully initialized.
   : io.taskack.valid <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException:  : [module SinkC]  Reference io is not fully initialized.
   : io.alloc.bits.isBop <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException:  : [module MSHR]  Reference io is not fully initialized.
   : io.tasks.source_b.bits.alias[1] <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException:  : [module MSHR]  Reference io is not fully initialized.
   : io.tasks.source_b.bits.alias[0] <= VOID
firrtl.passes.PassException: 5 errors detected!
1 targets failed
XiangShan.runMain subprocess failed
make: *** [Makefile:65: build/XSTop.v] Error 1

尝试过两个编译环境，产生的错误都一样： I have tried two different compilation environments, and the same errors occurred:

Verilator 5.025 devel rev v5.024-69-g7c9fa8647 + mill 0.9.8
Verilator 4.218 2022-01-17 rev v4.218 + mill 0.9.8

Tang-Haojin commented 1 month ago

You may try not to modify class DefaultConfig or delete FPGAConfig, and use make verilog CONFIG=FPGAConfig. It seems that this is already an FPGA-adapted config and you can use it.

xuyb1999 commented 1 month ago

I have tried to use the original FPGAConfig, and it passes make verilog CONFIG=FPGAConfig. But when I use OpenXiangShan/env-scripts (commit ID 506e9e5) to generate the bitstream for Nanhu-V2.1, the procedure fails at synthesis.

Here is the output errors of the synthesis runme.log:

WARNING: [Synth 8-7071] port 'SOC_M_AXI_arregion' of module 'jtag_ddr_subsys_wrapper' is unconnected for instance 'U_JTAG_DDR_SUBSYS' [/nfs/home/user/Workspace/env-scripts/xs_nanhu_fpga/src/rtl/xs_core_def_xdma.v:1366]
WARNING: [Synth 8-7071] port 'SOC_M_AXI_awregion' of module 'jtag_ddr_subsys_wrapper' is unconnected for instance 'U_JTAG_DDR_SUBSYS' [/nfs/home/user/Workspace/env-scripts/xs_nanhu_fpga/src/rtl/xs_core_def_xdma.v:1366]
WARNING: [Synth 8-7023] instance 'U_JTAG_DDR_SUBSYS' of module 'jtag_ddr_subsys_wrapper' has 61 connections declared, but only 59 given [/nfs/home/user/Workspace/env-scripts/xs_nanhu_fpga/src/rtl/xs_core_def_xdma.v:1366]
INFO: [Synth 8-6157] synthesizing module 'XSTop_wrapper' [/nfs/home/user/Workspace/env-scripts/xs_nanhu_fpga/src/rtl/XSTop_wrapper.v:1]
ERROR: [Synth 8-439] module 'XSTop' not found [/nfs/home/user/Workspace/env-scripts/xs_nanhu_fpga/src/rtl/XSTop_wrapper.v:161]
ERROR: [Synth 8-6156] failed synthesizing module 'XSTop_wrapper' [/nfs/home/user/Workspace/env-scripts/xs_nanhu_fpga/src/rtl/XSTop_wrapper.v:1]
ERROR: [Synth 8-6156] failed synthesizing module 'xs_core_def' [/nfs/home/user/Workspace/env-scripts/xs_nanhu_fpga/src/rtl/xs_core_def_xdma.v:3]
ERROR: [Synth 8-6156] failed synthesizing module 'xs_fpga_top_debug' [/nfs/home/user/Workspace/env-scripts/xs_nanhu_fpga/src/rtl/xs_fpga_top_debug.v:5]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:14 ; elapsed = 00:00:32 . Memory (MB): peak = 4501.078 ; gain = 1486.586 ; free physical = 92541 ; free virtual = 139143
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
85 Infos, 28 Warnings, 0 Critical Warnings and 5 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Wed Jul 10 11:36:49 2024...

My procedures to use OpenXiangShan/env-scripts are as follows:

cd env-scripts/xs_nanhu_fpga
make update_core_flist CORE_DIR=`realpath ../../Nanhu-v2.1/build`
make nanhu CORE_DIR=`realpath ../../Nanhu-v2.1/build`
make bitsream CORE_DIR=`realpath ../../Nanhu-v2.1/build`

Many thanks to your kindly help!

xuyb1999 commented 1 month ago

Moreover, I have tried to modify the FPGAConfig to set AlwaysBasicDiff and sramClkDivBy2 to false, but the same synthesis errors still happen.

diff --git a/src/main/scala/top/Configs.scala b/src/main/scala/top/Configs.scala
index c10650129..89763c6c1 100644
--- a/src/main/scala/top/Configs.scala
+++ b/src/main/scala/top/Configs.scala
@@ -318,8 +318,17 @@ class DefaultConfig(n: Int = 1) extends Config(
 )

 class FPGAConfig(n: Int = 1) extends Config(
-  new WithNKBL3(2 * 1024, inclusive = false, banks = 4, ways = 8)
+  (new WithNKBL3(2 * 1024, inclusive = false, banks = 4, ways = 8)
     ++ new WithNKBL2(512, inclusive = false, banks = 2, alwaysReleaseData = true)
     ++ new WithNKBL1D(128)
-    ++ new BaseConfig(n)
+    ++ new BaseConfig(n)).alter((site, here, up) => {
+    case DebugOptionsKey => up(DebugOptionsKey).copy(
+      AlwaysBasicDiff = false
+    )
+    case SoCParamsKey => up(SoCParamsKey).copy(
+      L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy(
+        sramClkDivBy2 = false,
+      ))
+    )
+  })
 )

Tang-Haojin commented 1 month ago

Seems that it did not found XSTop module. You may rename generated XSTop.v to XSTop.sv and add it to the FPGA project manually.

xuyb1999 commented 1 month ago

Sorry for my late reply. I follow your instructions to rename XSTop.v to XSTop.sv, execute the procedures of env-scripts, and find XSTop.sv is already added to the FPGA project.

Then I try to update the out-of-date hierarchy in the vivado project by "hierarchy->reload->Hierarchy Update -> Automatical Update and Compile Order", and specify a new top module. However, no matter I select the xs_fpga_top_debug or bosc_XSTop, the same synthesis error will still occur.

Could this be due to the env-scripts version being incompatible with the current Nanhu-v2.1?

Tang-Haojin commented 1 month ago

Seems that the module in the Hierarchy is bosc_XSTop. Did you add prefix argument? If so, you may also change the module name in XSTop_wrapper.

xuyb1999 commented 1 month ago

By change the module name in OpenXiangShan/env-scripts, the bitstream of Nanhu-V2.1 is successfully generated.

Thank you for your kind help!

diff --git a/xs_nanhu_fpga/src/rtl/XSTop_wrapper.v b/xs_nanhu_fpga/src/rtl/XSTop_wrapper.v
index d300425..7fc6976 100755
--- a/xs_nanhu_fpga/src/rtl/XSTop_wrapper.v
+++ b/xs_nanhu_fpga/src/rtl/XSTop_wrapper.v
@@ -158,7 +158,7 @@ module XSTop_wrapper(
 assign cpu_to_soc = 32'h0;

-XSTop  u_XSTop(
+bosc_XSTop  u_XSTop(
   .memory_0_awready                (mem_core_awready )                        ,
   .memory_0_awvalid                (mem_core_awvalid )                        ,
   .memory_0_awid                   (mem_core_awid    )                          ,

OpenXiangShan / XiangShan

What is the stable version of Nanhu-V2 verified on FPGA? #3155

Before start

Describe the question