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OpenXiangShan / XiangShan

Open-source high-performance RISC-V processor
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timing(ICache): allow send MSHR response to (pre)fetch even when io.flush #3542

Closed ngc7331 closed 3 weeks ago

ngc7331 commented 2 months ago

Cut critical path io.flush -> mainPipe/prefetchPipe s2_miss -> s2_ready -> ftq ready for timing.

Now missUnit will still send response to mainPipe/prefetchPipe/wayLookup when io.flush or io.fencei is true.B, but unnecessary response will be dropped by mainPipe/prefetchPipe/wayLookup since their sx_valid is set to false at the moment, so no functional/performance change is expected.

XiangShanRobot commented 2 months ago
[Generated by IPC robot] commit: c96e53f3880767fc1a0f0ca9f64c460eb7dc7388 commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
c96e53f 1.855 0.460 2.695 1.186 2.822 2.490 2.401 0.919 1.379 1.454 3.362 2.751 2.418 3.212
master branch: commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
c8c4067 0.919
976c97c 2.695 1.186 0.919 1.379 3.362 3.212
9143e23 2.695 1.186 0.919 1.379 3.212
b30cb8b 1.865 0.460 2.695 1.186 2.822 2.490 2.401 0.919 1.379 1.454 3.362 2.751 2.418 3.212
a53daa0 1.855 0.460 2.695 1.186 2.822 2.490 2.401 0.919 1.379 1.454 3.362 2.751 2.418 3.212
8b2f7ab 1.865 0.460 2.695 1.186 2.822 2.490 2.401 0.919 1.379 1.454 3.362 2.751 2.418 3.212
dd286b6 0.460 2.695 1.186 2.822 2.490 2.401 0.919 1.379 1.454 3.362 2.751 3.212
e6f36bc 1.855 0.460 2.695 1.186 2.822 2.490 2.401 0.919 1.379 1.454 3.362 2.751 2.418 3.212
3088616 1.855 0.460 2.695 1.186 2.822 2.490 2.401 0.919 1.379 1.454 3.362 2.751 2.418 3.212
ngc7331 commented 1 month ago

Timing result is good and performance is unchanged, ready to merge.

Yan-Muzi commented 1 month ago

This PR should be merged to optimize timinig.