How did Xiangshan achieve 10Mhz uart_16550?

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Before start

• [X] I have read the XiangShan Documents. 我已经阅读过香山文档。
• [X] I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。
• [X] I have searched the previous discussions and did not find anything relevant. 我已经搜索过之前的 discussions，并没有找到相关的。

Describe you problem

如下图所示，uart_16550的axi clock frequency最低支持到25Mhz。但是我也成功跑通了xiangshan 10M的bitfile，我想了解是怎么修改的uart_16550才能够实现让其能够接收低于25M的主时钟？ As shown in the figure below, the minimum supported axi clock frequency of uart_16550 is 25Mhz. But I also successfully ran the xiangshan 10M bitfile. I want to know how to modify uart_16550 to enable it to receive the main clock below 25M?

What did you do before

as above

Environment

• XiangShan branch:
• XiangShan commit id:
• NEMU commit id:
• SPIKE commit id:
• Operating System:
• gcc version:
• mill version:
• java version:

Additional context

No response

[Tang-Haojin]

Excuse me for the late reply. We actually wire a seperate 50MHz clock over UART, which is not affected by core or SoC frequency.