It looks like Xiangshan didn't commit every instruction in Rob?

[zhangkanqi]

Before start

• [X] I have read the RISC-V ISA Manual and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册，这不是一个指令集相关的问题。
• [X] I have read the XiangShan Documents. 我已经阅读过香山文档。
• [X] I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。
• [X] I have searched the previous discussions and did not find anything relevant. 我已经搜索过之前的 discussions，并没有找到相关的。
• [X] I have reviewed the commit messages from the relevant commit history. 我已经浏览过相关的提交历史和提交信息。

Describe the question

Hi! When run a program with XiangShan emu, it seems Xiangshan didn't commit every instruction in Rob.

As shown in the waveform below, XiangShan commit pc=0x80601070, 0x80601080, 0x80601090, 0x80601044, 0x80601050 in Rob.

However, the commit instructions in spike are as follows:

So I wonder why there is such a difference in instruction commit behavior between XiangShan and Spike, and why XiangShan seems not to commit every instruction in the ROB.

• XIangShan: 49162c9ab67070931573c1d4a372e2c858a72716