OpenXiangShan / XiangShan

Open-source high-performance RISC-V processor
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fix(StoreQueue): commitLastFlow should be true when the port 1 has no exception #3704

Closed huxuan0307 closed 1 month ago

huxuan0307 commented 1 month ago

When an exception is thrown by vector store:

* If not the last flow triggers an exception, then pull up the vecExceptionFlag and do not allow subsequent flows to actually 
* write to the sbuffer, but can exit the queue from the sq normally.

* If it is the last flow that triggered the exception, then there is no need to pull up vecExceptionFlag.

The vecExceptionFlag affects the vecvalid signal passed into the sbuffer, and only when vecvalid is high can data actually be written to the sbuffer.

Based on the current ports of the sbuffer, we list the cases as shown in the implementation:

* When only the first port is valid, we only need to see if the first port is lastflow.

* When both ports are valid, we need to judge based on whether robidx is equal or not:
       * When equal, the first port is definitely not lastflow, so we only need to judge whether the second port is lastflow.

       * When unequal, the first port is definitely lastflow, so we need to pull up vecCommitLastFlow when the second port 
       * doesn't trigger an exception, and we need to judge whether the second port is lastflow when the second port triggers 
       * an exception.
XiangShanRobot commented 1 month ago
[Generated by IPC robot] commit: ddbcf477b81c43743d700fce72359fdfc9132fe3 commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
ddbcf47 1.924 0.450 2.701 1.198 2.812 2.465 2.403 0.914 1.394 1.626 3.424 2.745 2.428 3.271
master branch: commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
ea2894c 1.924 0.450 2.701 1.198 2.812 2.465 2.403 0.914 1.394 1.626 3.424 2.745 2.428 3.271
1bc48dd 1.924 0.450 2.701 1.198 2.812 2.465 2.403 0.914 1.394 1.626 3.424 2.745 2.428 3.271
8bc9063 1.936 0.450 2.701 1.198 2.812 2.465 2.403 0.914 1.394 1.626 3.424 2.745 2.428 3.271
9c5487c 1.924 0.450 2.701 1.198 2.812 2.465 2.403 0.914 1.394 1.626 3.424 2.745 2.428 3.271
a32bbcb 1.936 0.450 2.701 1.198 2.812 2.465 2.403 0.914 1.394 1.626 3.424 2.745 2.428 3.271
9abad71 1.924 0.450 2.701 1.198 2.812 2.465 2.403 0.914 1.394 1.626 3.424 2.745 2.428 3.271
be3320d 1.924 0.450 2.701 1.198 2.812 2.465 2.403 0.914 1.394 1.626 3.424 2.745 2.428 3.271
8a4dab4 1.924 0.450 2.701 1.198 2.812 2.465 2.403 0.914 1.394 1.626 3.424 2.745 2.428 3.271
00cefdf 1.924 0.450 2.701 1.198 2.812 2.465 2.404 0.914 1.394 1.626 3.424 2.745 2.428 3.271
b9a37d2 0.450 2.701 2.404 1.394 2.745