OpenXiangShan / difftest

Modern co-simulation framework for RISC-V CPUs
Mulan Permissive Software License, Version 2
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Rocket-chip difftest框架使用 #354

Closed wyz-icer closed 2 months ago

wyz-icer commented 2 months ago

我在使用rocket chip的 dev-difftest分支遇到如下error (1) 准备工程: https://github.com/OpenXiangShan/rocket-chip/tree/dev-difftest?tab=readme-ov-file (2) 配置riscv-gcc (3) 工程配置信息: cp1@cp1:~/rocket-chip$ git branch

cp1@cp1:~/rocket-chip$ git log -1 commit 82c0f3e03152b1851c6b505d98237d0b2dc05883 (HEAD -> dev-difftest, origin/dev-difftest) Author: Yinan Xu xuyinan@ict.ac.cn Date: Sun Apr 21 21:04:22 2024 +0800

Bump Chisel 6.3.0 and DiffTest

(4)生成verilog报错: make verilog cd /home/cp1/rocket-chip && mill -i emulator[freechips.rocketchip.system.TestHarness,freechips.rocketchip.system.DefaultConfig].mfccompiler.compile [206/206] emulator[freechips.rocketchip.system.TestHarness,freechips.rocketchip.system.DefaultConfig].mfccompiler.compile 1 targets failed emulator[freechips.rocketchip.system.TestHarness,freechips.rocketchip.system.DefaultConfig].mfccompiler.compile java.io.IOException: Cannot run program "firtool" (in directory "/home/cp1/rocket-chip/out/emulator/freechips.rocketchip.system.TestHarness/freechips.rocketchip.system.DefaultConfig/mfccompiler/compile.dest"): error=2, 没有那个文件或目录 java.base/java.lang.ProcessBuilder.start(ProcessBuilder.java:1128) java.base/java.lang.ProcessBuilder.start(ProcessBuilder.java:1071) os.proc.proc$lzycompute$1(ProcessOps.scala:123) os.proc.proc$1(ProcessOps.scala:122) os.proc.spawn(ProcessOps.scala:129) os.proc.call(ProcessOps.scala:87) millbuild.build$Emulator$mfccompiler$.$anonfun$compile$3(build.sc:225) java.io.IOException: error=2, 没有那个文件或目录 java.base/java.lang.ProcessImpl.forkAndExec(Native Method) java.base/java.lang.ProcessImpl.(ProcessImpl.java:340) java.base/java.lang.ProcessImpl.start(ProcessImpl.java:271) java.base/java.lang.ProcessBuilder.start(ProcessBuilder.java:1107) java.base/java.lang.ProcessBuilder.start(ProcessBuilder.java:1071) os.proc.proc$lzycompute$1(ProcessOps.scala:123) os.proc.proc$1(ProcessOps.scala:122) os.proc.spawn(ProcessOps.scala:129) os.proc.call(ProcessOps.scala:87) millbuild.build$Emulator$mfccompiler$.$anonfun$compile$3(build.sc:225) make: *** [Makefile:73:verilog] 错误 1

这里没看找到 compile.dest的生成条件 麻烦帮忙确认下rocket-chip 的dev-difftest 分支目前是否正常可用!

poemonsense commented 2 months ago

Chisel requires a tool called firtool to convert the design to systemverilog/verilog. Latest Chisel versions use the firtool-resolver (https://github.com/chipsalliance/chisel/pull/3719) to automatically download and maintain the tool.

We can confirm that this issue is unrelated to difftest, and the rocket-chip demo at dev-difftest can be successfully built. Our CI verifies this: https://github.com/OpenXiangShan/difftest/actions/runs/8828829831/job/24238617719.

To fix the issue, you may check your network connections and rebuild your project after cleaning all build files. If everything you tried does not work, please reach out to rocket-chip or Chisel projects for help.

Since this issue is not related to difftest, we are closing this issue now.