Bump spike ref in ready-to-run

[NewPaulWalker]

• spike commit: 24bae53cf2cce375a58541e33cc1dd7ee8144da8
• spike config: CPU=XIANGSHAN

Including:

• fix(tinfo): CPU_XIANGSHAN's Trigger Module support Mcontrol6.
• Work if tcontrol doesn't exist.
• Make allow_action() take proc instead of state
• triggers: Move allow_action() into common_match()
• Only implement one solution for native triggers.
• fix(diff): Donot diff for tcontrol.
• fix(tdata1): CPU_XIANGSHAN do not implement hit bit in tdata1.
• fix(medeleg): In first implement of prevent reentrancy, BP bit in medeleg is writable.
• fix(vleff): reduce VL and donot raise BP exception if trigger fired on a later element.