make verilog err

[thrivemao]

Hi,请教一下这个问题 ====== Non-inclusive L3 (1.5MB * 4-bank) prefetch: false ====== bankBits: 2 sets:4096 ways:6 blockBytes:64 [client] size:512.0KB [client] sets:1024 ways:8 blockBytes:64 usr/preferCache: (1-bit) echo/blockisdirty: (1-bit) clientBits: 1 Data ECC bits:8 Tag ECC bits:6 Tag ECC bits:6 clientBits: 1 Data ECC bits:8 Tag ECC bits:6 Tag ECC bits:6 clientBits: 1 Data ECC bits:8 Tag ECC bits:6 Tag ECC bits:6 clientBits: 1 Data ECC bits:8 Tag ECC bits:6 Tag ECC bits:6 0 <= L2 1 <= dma ID#0 2 <= dma ID#1 3 <= debug 1 targets failed XiangShan.runMain subprocess failed make: *** [Makefile:75：build/XSTop.v] 错误 1

是因为submodule不全的原因还是其他原因