make verilog error: type AffectsChiselPrefix is not a member of package chisel3.experimental

[gaohy1003]

/xs-env/XiangShan$ make init git submodule update --init cd rocket-chip && git submodule update --init api-config-chipsalliance hardfloat /xs-env/XiangShan$ make verilog mkdir -p build time -a -o ./build/time.log mill -i XiangShan.runMain top.TopMain -td build \ --config DefaultConfig \ --infer-rw --repl-seq-mem -c:top.TopMain:-o:build/XSTop.v.conf --gen-mem-verilog full \ --num-cores 1 \ --disable-all --remove-assert --fpga-platform [56/214] hardfloat.compile [info] compiling 20 Scala sources to xs-env/XiangShan/out/foreign-modules/rocket-chip/hardfloat/hardfloat/compile/dest/classes ... [error] ## Exception when compiling 20 sources to xs-env/XiangShan/out/foreign-modules/rocket-chip/hardfloat/hardfloat/compile/dest/classes [error] scala.reflect.internal.Types$TypeError: type AffectsChiselPrefix is not a member of package chisel3.experimental [error] [error] 1 targets failed hardfloat.compile scala.reflect.internal.Types$TypeError: type AffectsChiselPrefix is not a member of package chisel3.experimental make: *** [Makefile:75: build/XSTop.v] Error 1

[SophistCedar]

I met the same question. Have you fix this one?

[Guo-HY]

I met the same question. Have you fix this one?

you can enter the XiangShan directory and checkout to the latest version of XiangShan on master branch. And pay attention to all submodules version of XiangShan, they should same with XiangShan repo on github

[SophistCedar]

I met the same question. Have you fix this one?

you can enter the XiangShan directory and checkout to the latest version of XiangShan on master branch. And pay attention to all submodules version of XiangShan, they should same with XiangShan repo on github

HI, i run below command in Xiangshan directory. But no improvements.

weincai@jxing-Ubuntu-01:~/VI/chisel-xs-env/xs-env/XiangShan$ git submodule update --init --recursive --force Submodule path 'difftest': checked out '9b17ca076ad76720bfa740cae2765a3a1dee3758' Submodule path 'fudian': checked out '3dd05b088179e6571d14436acc5d02dd08390edf' Submodule path 'fudian/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037' Submodule path 'fudian/berkeley-testfloat-3': checked out '06b20075dd3c1a5d0dd007a93643282832221612' Submodule path 'huancun': checked out 'f2da3bef292974ea60d85593452cc046ad479022' Submodule path 'huancun/rocket-chip': checked out '85f319c62fecc1fbcbfb67648dcb9747d71ebe49' Submodule path 'huancun/rocket-chip/api-config-chipsalliance': checked out 'fd8df1105a92065425cd353b6855777e35bd79b4' Submodule path 'huancun/rocket-chip/hardfloat': checked out '70455e53f233a06cb5a342d125e22b7b1505c271' Submodule path 'huancun/rocket-chip/hardfloat/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037' Submodule path 'huancun/rocket-chip/hardfloat/berkeley-testfloat-3': checked out '06b20075dd3c1a5d0dd007a93643282832221612' Submodule path 'huancun/rocket-chip/torture': checked out '99d8b2b441ecaa18b852505bb7718ee04e2753f5' Submodule path 'huancun/rocket-chip/torture/env': checked out 'ce70afbf50a203be04bc326326cfa75831fe7f5d' Submodule path 'ready-to-run': checked out 'ec61625c166424bd423327d9607e0df3803a20e1' Submodule path 'rocket-chip': checked out '85f319c62fecc1fbcbfb67648dcb9747d71ebe49' Submodule path 'rocket-chip/api-config-chipsalliance': checked out 'fd8df1105a92065425cd353b6855777e35bd79b4' Submodule path 'rocket-chip/hardfloat': checked out '70455e53f233a06cb5a342d125e22b7b1505c271' Submodule path 'rocket-chip/hardfloat/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037' Submodule path 'rocket-chip/hardfloat/berkeley-testfloat-3': checked out '06b20075dd3c1a5d0dd007a93643282832221612' Submodule path 'rocket-chip/torture': checked out '99d8b2b441ecaa18b852505bb7718ee04e2753f5' Submodule path 'rocket-chip/torture/env': checked out 'ce70afbf50a203be04bc326326cfa75831fe7f5d'

weincai@jxing-Ubuntu-01:~/VI/chisel-xs-env/xs-env/XiangShan$ make verilog mkdir -p build time -a -o ./build/time.log mill -i XiangShan.runMain top.TopMain -td build \ --config DefaultConfig \ --infer-rw --repl-seq-mem -c:top.TopMain:-o:build/XSTop.v.conf --gen-mem-verilog full \ --num-cores 1 \ --disable-all --remove-assert --fpga-platform [56/214] hardfloat.compile [info] compiling 20 Scala sources to /home/weincai/VI/chisel-xs-env/xs-env/XiangShan/out/foreign-modules/rocket-chip/hardfloat/hardfloat/compile/dest/classes ... [error] ## Exception when compiling 20 sources to /home/weincai/VI/chisel-xs-env/xs-env/XiangShan/out/foreign-modules/rocket-chip/hardfloat/hardfloat/compile/dest/classes [error] scala.reflect.internal.Types$TypeError: type AffectsChiselPrefix is not a member of package chisel3.experimental [error] [error]
1 targets failed hardfloat.compile scala.reflect.internal.Types$TypeError: type AffectsChiselPrefix is not a member of package chisel3.experimental make: *** [Makefile:75: build/XSTop.v] Error 1

[SophistCedar]

git clone --recurse-submodules https://github.com/OpenXiangShan/xs-env.git

I also try above command to get all submodule and nested modules when firstly clone the repo. And the command running smoothly, no network issue or other issues happened. So i think the code is complete. but sill the error info displayed.

[Guo-HY]

git clone --recurse-submodules https://github.com/OpenXiangShan/xs-env.git

I also try above command to get all submodule and nested modules when firstly clone the repo. And the command running smoothly, no network issue or other issues happened. So i think the code is complete. but sill the error info displayed.

I highly recommened you to delete XiangShan folder manually and "git clone git@github.com:OpenXiangShan/XiangShan.git" under xs-env folder. then enter the XiangShan folder and "git submodule update --init --recursive" please pay attention to the submodule version :

[SophistCedar]

Hi, i try run your suggestion. run commands as below in the directory xs-env.

rm -rf XiangShan git clone https://github.com/OpenXiangShan/XiangShan.git cd XiangShan git submodule update --init --recursive make verilog

The previous error gone. But a new error happened. Since the log is in much quantity, i only copy the last few lines of error info as below. ====== Non-inclusive L3 (1.5MB * 4-bank) prefetch: false ====== bankBits: 2 sets:4096 ways:6 blockBytes:64 [client] size:512.0KB [client] sets:1024 ways:8 blockBytes:64 usr/preferCache: (1-bit) echo/blockisdirty: (1-bit) clientBits: 1 Data ECC bits:8 Tag ECC bits:6 Tag ECC bits:6 clientBits: 1 Data ECC bits:8 Tag ECC bits:6 Tag ECC bits:6 clientBits: 1 Data ECC bits:8 Tag ECC bits:6 Tag ECC bits:6 clientBits: 1 Data ECC bits:8 Tag ECC bits:6 Tag ECC bits:6 0 <= L2 1 <= dma ID#0 2 <= dma ID#1 3 <= debug 1 targets failed XiangShan.runMain subprocess failed make: *** [Makefile:75: build/XSTop.v] Error 1

BTW, what do you mean "please pay attention to the submodule version" ? I cannot clearly understand this.

[Guo-HY]

Hi, i try run your suggestion. run commands as below in the directory xs-env.

rm -rf Xiangshan git clone https://github.com/OpenXiangShan/XiangShan.git cd Xiangshan git submodule update --init --recursive make verilog

The previous error gone. But a new error happened. Since the log is in much quantity, i only copy the last few lines of error info as below. ====== Non-inclusive L3 (1.5MB * 4-bank) prefetch: false ====== bankBits: 2 sets:4096 ways:6 blockBytes:64 [client] size:512.0KB [client] sets:1024 ways:8 blockBytes:64 usr/preferCache: (1-bit) echo/blockisdirty: (1-bit) clientBits: 1 Data ECC bits:8 Tag ECC bits:6 Tag ECC bits:6 clientBits: 1 Data ECC bits:8 Tag ECC bits:6 Tag ECC bits:6 clientBits: 1 Data ECC bits:8 Tag ECC bits:6 Tag ECC bits:6 clientBits: 1 Data ECC bits:8 Tag ECC bits:6 Tag ECC bits:6 0 <= L2 1 <= dma ID#0 2 <= dma ID#1 3 <= debug 1 targets failed XiangShan.runMain subprocess failed make: *** [Makefile:75: build/XSTop.v] Error 1

BTW, what do you mean "please pay attention to the submodule version" ? I cannot clearly understand this.

For make verilog error you can gain more information in this issue: https://github.com/OpenXiangShan/XiangShan/issues/837

（How much memory size do you have ? I think the error is may caused by your insufficient memory size)

" please pay attention to the submodule version " for example :

fudian is 3dd05b0, and when you enter fudian folder and use git log it should be like this:

the current HEAD point to 3dd05b0 , and this is same with XiangShan repo on gitHub

[SophistCedar]

Hi, i try run your suggestion. run commands as below in the directory xs-env. rm -rf Xiangshan git clone https://github.com/OpenXiangShan/XiangShan.git cd Xiangshan git submodule update --init --recursive make verilog The previous error gone. But a new error happened. Since the log is in much quantity, i only copy the last few lines of error info as below. ====== Non-inclusive L3 (1.5MB * 4-bank) prefetch: false ====== bankBits: 2 sets:4096 ways:6 blockBytes:64 [client] size:512.0KB [client] sets:1024 ways:8 blockBytes:64 usr/preferCache: (1-bit) echo/blockisdirty: (1-bit) clientBits: 1 Data ECC bits:8 Tag ECC bits:6 Tag ECC bits:6 clientBits: 1 Data ECC bits:8 Tag ECC bits:6 Tag ECC bits:6 clientBits: 1 Data ECC bits:8 Tag ECC bits:6 Tag ECC bits:6 clientBits: 1 Data ECC bits:8 Tag ECC bits:6 Tag ECC bits:6 0 <= L2 1 <= dma ID#0 2 <= dma ID#1 3 <= debug 1 targets failed XiangShan.runMain subprocess failed make: *** [Makefile:75: build/XSTop.v] Error 1 BTW, what do you mean "please pay attention to the submodule version" ? I cannot clearly understand this.

For make verilog error you can gain more information in this issue: OpenXiangShan/XiangShan#837

（How much memory size do you have ? I think the error is may caused by your insufficient memory size)

" please pay attention to the submodule version " for example : fudian is 3dd05b0, and when you enter fudian folder and use git log it should be like this: the current HEAD point to 3dd05b0 , and this is same with XiangShan repo on gitHub

My memory size is 32GB physical memory. Got the meaning of the submodule version meaning. Will check it later. Thanks for your explanation.

[SophistCedar]

Maybe it is indeed caused by the insufficient memory size. I check the memory usage when failed. The memory seems to be out of usage. shown as below.

1. I will change the JVM Xmx parameter to a small value instead of 64G, 64G is the JVM Xmx setting in my synced build.sc
2. I will try to increase my physical memory size, or increase the swap size for a work around.

Thanks again.

[SophistCedar]

I change the JVM Xmx setting to 24GB (physical memory size is 32GB) in build.sc. //override def forkArgs = Seq("-Xmx64G", "-Xss256m") override def forkArgs = Seq("-Xmx24G", "-Xss256m")

Now the compilation passed. And the compilation time cost is about 20min.

[poemonsense]

The issue is generally caused by multiple Chisel projects using different versions of Chisel. If you encounter any further issues, please feel free to re-open this issue.

For the memory usage, we'll soon upgrade to Chisel5 with CIRCT. It would use far less memory resources than the current Chisel3.