Host & Client: Implement using a bus transceiver in order to protect Pico and attached devices

[Tails86]

The Pico is not able to source or sink any more than 50 mA on the I/O. This isn't an issue unless a fault occurs which would kill the Pico. Using a 2-bit bus transceiver which could source/sink higher current value per pin would be beneficial. Selecting one with good transient voltage suppression is desired. The transceiver will need to switch from output to input and back within 1 microsecond, and it must be able to handle pulse widths of 150 ns.

This involves setting up 4 new outputs in order to select the external transceiver direction. The documentation must then be updated to provide this as an option.

[Tails86]

This seems like a good option to test with https://www.digikey.com/en/products/detail/texas-instruments/SN74AXCH2T45DCUR/12165180

[Tails86]

That chip works only when the "open line check" in MapleBus::writeInit() is disabled. This is because the chip has an embedded "Bus-Hold Latch" which is incompatible with weak pull-ups. There is a strong potential for the input to be latched low, and MapleBus will never write. I am looking for alternative chips.

[Tails86]

This could potentially be useful, but it has more IO than is needed: https://www.digikey.com/en/products/detail/texas-instruments/CD74HC243E/1506891 It also has a surface mount equivalent: https://www.digikey.com/en/products/detail/rochester-electronics-llc/CD74HC243M/11546734

[Tails86]

This is a better alternative from a different manufacturer: https://www.mouser.com/ProductDetail/Nexperia/74LVC2T45DC125?qs=jquClx72t9CXQGU9YSJngw%3D%3D

It looks similar to the original option, but it doesn't have the latching feature.

[Tails86]

It has occurred to me that the "H" in the chip number means latching. The following is the TI chip without latching. https://www.digikey.com/en/products/detail/texas-instruments/SN74AXC2T45QDCURQ1/15666789