Open chrishume opened 4 years ago
Agreed, and in fact I think our goal should be that they are all modeled behaviorally too.
I think I did what was necessary to model them behaviorally on O1, but I don't know if I spec tested it. I'll make sure they're modeled correctly on O2 and backfill to O1 if they're not already functional.
Why does the register use a different access
nomenclature than the bit field?
<spirit:access>read-write</spirit:access>
<spirit:reset>
<spirit:value>0x8000</spirit:value>
<spirit:mask>0xFFFFFFFF</spirit:mask>
</spirit:reset>
<spirit:field>
<spirit:name>second_bit</spirit:name>
<spirit:description></spirit:description>
<spirit:bitOffset>14</spirit:bitOffset>
<spirit:bitWidth>1</spirit:bitWidth>
<spirit:access>rw</spirit:access>
I believe it's because the register isaa conglomeration of different bit field access types. A register can qualify as ReadWrite because it contains a mix of ReadOnly and WriteOnly bits.
On Tue, Dec 31, 2019, 10:24 AM info-rchitect notifications@github.com wrote:
Why does the register use a different access nomenclature than the bit field?
<spirit:access>read-write</spirit:access> <spirit:reset> <spirit:value>0x8000</spirit:value> <spirit:mask>0xFFFFFFFF</spirit:mask> </spirit:reset> <spirit:field> <spirit:name>second_bit</spirit:name> <spirit:description></spirit:description> <spirit:bitOffset>14</spirit:bitOffset> <spirit:bitWidth>1</spirit:bitWidth> <spirit:access>rw</spirit:access>
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I believe it's because the register isaa conglomeration of different bit field access types. A register can qualify as ReadWrite because it contains a mix of ReadOnly and WriteOnly bits. …
Thx Chris. I guess I just wondered why it didn't use rw
?
Basically expand what's there already (RO, RW, WO, WONCE, RWONCE) to support the full list of access types that IP-XACT supports (20-something, IIRC).
I'll be glad to do the work for this, as I did it on O1.