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Origen-SDK / origen_sim

Plugin to enable Origen patterns to be run in a dynamic Verilog simulation
MIT License
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Sim Delay discussion #23

Closed priyavadan closed 5 years ago

priyavadan commented 6 years ago

@ginty based on our discussions from today. Is it possible to have the sim_delay method restore the pin to the original state when the block is done? Currently we have to do the following in the code for stuff to work as expected:


        tester.sim_delay :erase_command do
          dut.pin(:done).assert!(1)
        end

        dut.pin(:done).dont_care!

Thanks!!

ginty commented 5 years ago

Fixed by #24