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Origen-SDK / origen_sim

Plugin to enable Origen patterns to be run in a dynamic Verilog simulation
MIT License
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Prevent sim monitor stopped errors during legal shutdown #28

Closed ginty closed 5 years ago

ginty commented 5 years ago

Under some conditions simulations would pass but would show the following error in the log near the end:

[ERROR]    1234.567[0.000] || The simulation monitor has stopped unexpectedly!

This appears to be caused by the simulation monitor (this process) aborting in an un-controlled manner once the simulation has completed and been told to stop.

While the exact sequence of events to cause this is not understood, this patch will inhibit the error message being written if it occurs after the simulation has completed successfully and been told to stop.

Note that there are effectively two parallel implementations of this fix since OrigenSim currently works around the fact that the byebug debugger does not keep parallel threads running asynchronously at a breakpoint, and a forked process is used instead. Communicating with such a forked process is tricky and achieved here by writing a temporary file to let it know that the simulation has finished and it should not display this meaningless error.

coreyeng commented 5 years ago

Thanks! Like you said, this was one of oddities that'd pop up every now and again but was difficult to reproduce so thanks for taking care of it.