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Origen-SDK / origen_sim

Plugin to enable Origen patterns to be run in a dynamic Verilog simulation
MIT License
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Name of 'module' needs to change when filename name is changed #31

Open chrisnappi opened 5 years ago

chrisnappi commented 5 years ago

@coreyeng Fairly certain that when we specify --verilog_top_output_name the name of the module in the file needs to be changed to match.

ginty commented 5 years ago

I think this may be fixed by https://github.com/Origen-SDK/origen_sim/pull/43