Origen-SDK / origen_sim

Plugin to enable Origen patterns to be run in a dynamic Verilog simulation
MIT License
1 stars 4 forks source link

Reg fail info #42

Closed pderouen closed 5 years ago

pderouen commented 5 years ago

This is an update to handle cases where a failing bit is outside of the bounds of the register being read. I also added in mapping of ruby syntax to verilog syntax to fix some failing spec tests.