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Origen-SDK / origen_sim

Plugin to enable Origen patterns to be run in a dynamic Verilog simulation
MIT License
1 stars 4 forks source link

Timing update #44

Closed pderouen closed 5 years ago

pderouen commented 5 years ago

If there was only 1 drive event, previously the drive would always be placed at time 0 of the cycle unless the previous cycle was not driving. This fixes that bug (I believe).

pderouen commented 5 years ago

Loads of fun!