Closed gregory38 closed 7 years ago
Remainder until I manage to open a GCC issue (account creation is blocked due to spam).
Here a snippet of the bug:
The bug is a 4.9/5/6/7 regression on AVX2 handling.
// g++ -O2 -c ./intrin-avx2.c -std=c++11 -mavx2 -save-temps #include <immintrin.h> __m256i m; __m128i extract(__m128i minmax) { int lod = _mm_cvtsi128_si32(_mm256_castsi256_si128(m)); return _mm_srli_epi16(minmax,lod); }
// It will compile (GCC 4.9) to those 2 instructions (not intel syntax, destination is on the right). vmovdqa m(%rip), %xmm1 // Bug is here %xmm1 ough to contains only 32 bits of data. [64:32] bits ought to be 0. vpsrlw %xmm1, %xmm0, %xmm0
Note PR #1876 added a workaround to avoid the issue.
Turtleli mentioned there 6.3 looks fine.
I mentioned the workaround worked fine.
Bug confirmed :smile: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80286
Remainder until I manage to open a GCC issue (account creation is blocked due to spam).
Here a snippet of the bug:
The bug is a 4.9/5/6/7 regression on AVX2 handling.