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Incompatible Timesharing System
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TST8K #1867

Open larsbrinkhoff opened 4 years ago

larsbrinkhoff commented 4 years ago

Inside the archive IMLAC; IML DEVICE:
TOGGLE INFO some tests meant to be toggled in
TST8K4 1 checks the Dynamic Modeling display modification

larsbrinkhoff commented 4 years ago

Comments from @jdersch:

Took a look at the TST8K1 test, and something odd's going on. The following line:

DADR ; 107/ 004001 ; turn on 8k addressing

Claims to be turning on 8K addressing but per the documentation, it does nothing at all (it should effectively be a no-op because the F field is 0). See pg. 46 of http://bitsavers.org/pdf/imlac/PDS-1D_ProgrammingGuide.pdf. Per the docs it should be 004011...

I'm still puzzled. If I modify the emulator to assume that 004001 causes the display processor to start addressing in the top 4K of memory after the next DJMP, the TST8K1 diagnostic works, but I still have to correct the DJMP instruction since it's off by one -- not sure what causes that; the listing in TOGGLE.INFO clearly shows both the DJMP (at 113) and the jump's target are correct; when the binary is loaded, everything in the upper page is offset by 1 word.

larsbrinkhoff commented 4 years ago

I'm testing this program:

LOC 100

START:  LAW DLIST       ; display list address
        DLA             ; load dpc
        DON             ; start display
        DSN             ; display off?
        JMP .-1         ; no
        JMP START       ; yes, loop

DLIST:  DHVS 1          ; startup
MODE:   DADR            ; turn on 8k addressing
        DGD             ; part of set point
        DLXA 1000       ; set point to center
        DLYA 1000       ; of screen
        DJMP HI         ; jump to high core
        DHLT            ; halt

LOC .+10000

HI:     DDSP            ; display dot
        DHLT            ; halt

END START

Or in octal:


START/   DDYM+6   =4106   
START+1/   DLA   =1003   
START+2/   DON   =3100   
START+3/   DSN   =102010   
START+4/   10103   
START+5/   10100   
DLIST/   DHVS+1   =6005   
DLIST+1/   DADR   =4001   
DLIST+2/   DGD   =77771   
DLIST+3/   11000   
DLIST+4/   21000   
DLIST+5/   160115   
DLIST+6/   0   
HI/   DDSP   =4020   .=10115   
HI+1/   0
larsbrinkhoff commented 4 years ago

Stepping through this, I see the main processor is looping 100 to 105 and back.

The display procesor is running from 106 to 116 and stops there until restarted by the main processor.

I think sImlac says the DJMP didn't assemble right:


>disassemble DisplayProcessor 106 20
000106\006005 DHVC ,DHLT DSTS 1
000107\004001 DHLT 
000110\077771 SGR1 000001 
000111\011000 DLXA 001000 
000112\021000 DLYA 001000 
000113\160115 DJMP 000115 
000114\000000 DDYM DLPN 0
000115\000000
larsbrinkhoff commented 4 years ago

Correction, I think it's right. The leftmost 1 in 160115 is the high address bit.

larsbrinkhoff commented 4 years ago

It seems the MIT 8K addressing modification is not the same as the official Imlac 8K addressing. The MIT DADR instruction is 004001 which would be a nop according to the PDS-1 manual. MIT's assembler defines:

IRP     .DOP,,[DLXA,DLYA,DJMS,DJMP]
DEFINE  .DOP    (.DARG)
.!.DOP!\<<.DARG>&7777>\<<<.DARG>_3>&100000&<<.ADDR.>_15.>> TERMIN
TERMIN

This defines DLXA, DLYA, DJMP, and DJMP to take an additional address bit from bit 0 of the instruction which would normally be unused. This is controlled by .ADDR.