search

PKU-IDEA / OpenPARF

🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
BSD 3-Clause "New" or "Revised" License
107 stars 13 forks source link

Questions for the structure of x_arch.xml #1

Closed Ahorns closed 1 year ago

Ahorns commented 1 year ago

May I ask why the structure of your architecture is different with others structure such like ultrascale_ispd.xml? And may I ask how you converted that or made it? Thank you so much!

magic3007 commented 1 year ago

Thanks for highlighting this issue. I assume you refer to https://raw.githubusercontent.com/verilog-to-routing/vtr-verilog-to-routing/master/vtr_flow/arch/ispd/ultrascale_ispd.xml in the VTR repo for ultrascale_ispd.xml. Our x_arch is derived from the ISPD 2016 & 2017 contests with Xilinx Ultrascale architecture, so the placement architecture is almost the same as ultrascale_ispd. However, x_arch detailed the routing architecture from industrial practice, which is not included in ultrascale_ispd.

The detailed routing architecture is described in the paper A Robust FPGA Router with Concurrent Intra-CLB Rerouting (ASPDAC'2023). We ran all the evaluations under the same architecture and settings for fair comparison. Thank you for bringing this to our attention and for your contribution to improving our work.

Ahorns commented 1 year ago

I appreciate your timely response which helps me a lot to solve the question. Thanks a lot!