This pull request introduces a multi-die placement feature, aiming at this stage to optimize the SLL (Super Long Line) counts. It extends the tool's capabilities to efficiently handle modern FPGA designs, marking a significant improvement in design automation.
Features
Implements the multi-die placement algorithm as proposed in the LEAPS publication. This algorithm focuses on optimizing FPGA placement to reduce the number of SLLs, crucial for enhancing timing performance.
Introduces highly customizable multi-die FPGA architecture configuration options, enabling users to quickly verify and evaluate support for various multi-die FPGA architectures.
Includes comprehensive unit tests and detailed documentation for the new feature, ensuring robustness and ease of use for future developers and users.
Request for Feedback
Thank you for considering this contribution. I'm open to feedback and any further discussions on improving this feature.
Overview
This pull request introduces a multi-die placement feature, aiming at this stage to optimize the SLL (Super Long Line) counts. It extends the tool's capabilities to efficiently handle modern FPGA designs, marking a significant improvement in design automation.
Features
Request for Feedback
Thank you for considering this contribution. I'm open to feedback and any further discussions on improving this feature.