Resolve performance regression

POETSII / tinsel

Manythread RISC-V overlay for FPGA clusters

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Resolve performance regression #93

Closed mn416 closed 4 years ago

mn416 commented 4 years ago

Allow full-throughput of RAM requests from the caches again. Silly oversight.

Also: throttle RAM requests from the ProgRouter for fairness. Not clear how important this is, but the ProgRouter uses bursts so (without throttling) would be able to get more bandwidth than the caches.