Open gut opened 8 years ago
A motivation behind this issue:
As you can see, the "dot variant" takes much longer than the one without it. This SF liveness pass would improve performance for these instructions.
Bonus: compare is very expensive:
Source: https://www.setphaserstostun.org/power8/POWER8_UM_v1.3_16MAR2016_pub.pdf
ps: this idea is already implemented for ARM:
" Strength reduction on flag-setting instructions. On x64, arithmetic and bitwise operations always set the status flags, but this is not the case on ARM. With some better analysis of defs and uses of virtual SF registers, we can avoid unnecessary flag-setting on ARM (and other architectures with multiple strengths of arithmetic instructions)."
http://hhvm.com/blog/2017/03/09/how-the-cyber-elephant-got-his-arm.html
https://reviews.facebook.net/D50415#inline-359421
then new arithmetic vasms that doesn't need to handle the SF (like addi) could be used for sure.