Hi there,
Thanks for providing such a great paper and code. I have read your paper in arXiv, but still have some questions. Could you explain it a little bit for me?
About the article:
1) How did you compare the prediction accuracy to chips like Eyeriss and TPU? I believe the source code of them are not available in public.
2) How did you consider the data orchestration and memory bank conflict?
3) Does ONNXim target to systolic array (WS/IS/OS) only?
About the code:
4) Is there optimizer for optimal mapping? If yes, could you let me know where it is in code?
5) It is mentioned in II-A, "the tile size are chosen using heuristics form prior work [8]". So the tile size calculator in ONNXim is exactly to the one from Gemmini?
6) How did you calculate the data manipulation time (e.g. from global buffer to local buffer)?
Hi there, Thanks for providing such a great paper and code. I have read your paper in arXiv, but still have some questions. Could you explain it a little bit for me?
About the article: 1) How did you compare the prediction accuracy to chips like Eyeriss and TPU? I believe the source code of them are not available in public. 2) How did you consider the data orchestration and memory bank conflict? 3) Does ONNXim target to systolic array (WS/IS/OS) only?
About the code: 4) Is there optimizer for optimal mapping? If yes, could you let me know where it is in code? 5) It is mentioned in II-A, "the tile size are chosen using heuristics form prior work [8]". So the tile size calculator in ONNXim is exactly to the one from Gemmini? 6) How did you calculate the data manipulation time (e.g. from global buffer to local buffer)?