Open CE1CECL opened 2 years ago
Can you elaborate a bit on this? I'm roughly aware of Coreboot supporting AMD SoCs by including PSP binaries. I've seen coreboot has their own tool for building valid PSP firmware directories, is that correct?
They do have a tool to build the blobs, from the fw.cfg, but im trying to port my hp pc to coreboot, they do mention raven1 in amd_blobs repo, but dont actually have the bins anywhere.
Understood. I'm afraid, unless somebody else would heavily contribute to PSPTool, the creation of Coreboot artifacts for production use is out of scope of PSPTool. Our goal so far has only been reverse engineering of (proprietary, UEFI) firmware to enable security research.
That being said, if you're able to use PSPTool to extract binaries that can be used with Coreboot tools and there's only minor format changes needed, I might be able to help.
its worth mentioning that i cant use a coreboot rom with psptool, do you know why? ive also since opened a "issue" with amd firmware_binaries repo https://github.com/amd/firmware_binaries/pull/4
@cwerling I just found out that you can just replace the BIOS entry, with something like coreboot or other, am I correct? After all, not everything can be open source sadly but its better than nothing.
@CE1CECL To my knowledge, no AMD system of the previous years is currently supported by coreboot. The fact that the initial boot stage of the x86 can be referenced in the PSP file system serves some of the more integrated systems (like Chromebooks, Tesla Plaid) to enable the PSP to authenticate the first x86 boot stage. Unfortunately, this is something only OEMs with special access to AMD documentation can properly configure/implement.
Other than that, there were some news recently about AMD server boards getting access to an open silicon initialization library: https://www.phoronix.com/news/AMD-openSIL-Open-Source
Padding_Non-empty_Padding.pad.tar.gz Question: For files pad1 and pad3, what are they? Are they Part of the PSP, because pad2 for sure is but I can't figure out the other padding's on what they actually are and do, unless its just UEFI data?
For Reference use https://github.com/CE1CECL/coreboot/blob/ce1cecl/src/soc/amd/picasso/fw.cfg