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PacktPublishing / Learn-FPGA-Programming

Learn FPGA Programming, published by Packt
MIT License
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FAIL: AND Gate mismatch #5

Closed jjliuhk closed 1 year ago

jjliuhk commented 2 years ago

Hi,

I am reading your book and I am trying to run simulation on Vivado 2022.1 for CH1's logic_ex example. However, it fails on checking and show "FAIL: AND Gate mismatch". I tried to set Project device to Nexys A7-100T and Arty A7-100, and the results are same. I wonder if you may advise.

jjliuhk commented 2 years ago

I managed to install Vivado 2020 and it can run simulation without the error on Vivado 2022. I wonder if anyone can tell me where to find information about updating Vivado 2020 project to 2022?

asicguy commented 2 years ago

Sorry I haven't looked at this yet. I believe this was reported before. The reason is due to a change in the way the vivado simulator works and delta events. On reflection, the newer version may be handling the events more correctly and I'll need to look at adding a delay, something which I don't like doing as it's bad practice in synchronous designs and I didn't want to muddy the waters. For now, all the simulations will work in the version specified for the book and I'll need to see what I can do to bring everything forward.

nithikpackt commented 1 year ago

Thank you @asicguy for your response. Closing the issue, for now, Please reopen in case of any update to the issue.