Paebbels / pyVHDLParser

Streaming based VHDL parser.
https://paebbels.github.io/pyVHDLParser/
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Are std_logic_vectors not supported? #13

Open Brandon-Valley opened 3 years ago

Brandon-Valley commented 3 years ago

Greetings,

Python I am using:


vhdl_file_path = "C:\\projects\\auto_wapper\\example\\demo.vhd"

# Open a source file
with open(vhdl_file_path, 'r') as fileHandle:
    content = fileHandle.read()

from pyVHDLParser.Token.Parser      import Tokenizer
from pyVHDLParser.Blocks            import TokenToBlockParser
from pyVHDLParser.Base              import ParserException

# get a token generator
tokenStream = Tokenizer.GetVHDLTokenizer(content)
# get a block generator
blockStream = TokenToBlockParser.Transform(tokenStream)

from pyVHDLParser.Blocks            import MetaBlock
for block in MetaBlock.BLOCKS:
        try:
            block.__cls_init__()
        except AttributeError:
            pass

try:
    for block in blockStream:
        print("{block!s}".format(block=block))
    for token in block:
        print("  {token!s}".format(token=token))
except ParserException as ex:
    print("ERROR: {0!s}".format(ex))
except NotImplementedError as ex:
    print("NotImplementedError: {0!s}".format(ex))    

When run on this .vhd file, everything works fine:


entity demo is
    port (
        a    : in  std_logic;
        -- b    : out std_logic_vector( 15 downto 0 );
        c    : out std_logic
    );
end entity demo;

But when I uncomment the line with the std_logic_vector as shown below, I receive the following error.


entity demo is
    port (
        a    : in  std_logic;
        b    : out std_logic_vector( 15 downto 0 );
        c    : out std_logic
    );
end entity demo;
pydev debugger: starting (pid: 18620)
[StartOfDocumentBlock]
[LinebreakBlock                                                                                                    at (line:   1, col:  1) .. (line:   1, col:  1)]
[Entity.NameBlock                                   'entity demo is'                                               at (line:   2, col:  1) .. (line:   2, col: 15)]
[LinebreakBlock                                                                                                    at (line:   2, col: 15) .. (line:   2, col: 15)]
[IndentationBlock                                    length=4 (4)                                                  at (line:   3, col:  1) .. (line:   3, col:  4)]
[PortList.OpenBlock                                 'port ('                                                       at (line:   3, col:  5) .. (line:   3, col: 10)]
[LinebreakBlock                                                                                                    at (line:   3, col: 11) .. (line:   3, col: 11)]
[IndentationBlock                                    length=8 (8)                                                  at (line:   4, col:  1) .. (line:   4, col:  8)]
[PortList.PortListInterfaceSignalBlock              'a    : in  std_logic'                                         at (line:   4, col:  9) .. (line:   4, col: 29)]
[PortList.DelimiterBlock                            ';'                                                            at (line:   4, col: 29) .. (line:   4, col: 29)]
[LinebreakBlock                                                                                                    at (line:   4, col: 30) .. (line:   4, col: 30)]
[IndentationBlock                                    length=8 (8)                                                  at (line:   5, col:  1) .. (line:   5, col:  8)]
ERROR: Expected ';', ':=' or whitespace after subtype indication.

Am I doing something wrong? Any recomendations on how I should proceed? Any and all assistance is greatly appreciated! :)

Paebbels commented 3 years ago

The log shows the following:

in the state where the parser currently is, it expects either a semicolon or := to assign a default value to a port. This means, the parser lost the information, it already consumed a ; before the linebreak and/or the indentation. That's why it asks again as if it would still stand in the line of a.

Please try this:

entity demo is
    port (
        a    : in  std_logic; -- dummy
        b    : out std_logic_vector( 15 downto 0 ); -- dummy
        c    : out std_logic
    );
end entity demo;
Paebbels commented 3 years ago

I added a first set of test cases for port lists in a087e043. The second test shows a Last token is not connected to the current token. error when checking the linked data structures.

The test case could pass with: port1 : bit;port2 : boolean but fails with port1 : bit; port2 : boolean note the space after ; between two ports.