cooperation

[Nic30]

Hello,

I am working on very similar project https://github.com/Nic30/hdlConvertor . I am using parser/lexer generated from grammar written in ANTLR4 and representing HDL by json like objects. And I have a library for generating of VHDL (not only) https://github.com/Nic30/HWToolkit .

Are you interested in cooperation?

[Paebbels]

Hello Nic,

I saw your postings at GHDL so I'm aware of your project :). I'm not sure if an ANTLR4 approach would fit my needs, because my latest information is that the freely available ANTLR4 grammar for VHDL is not complete. From Sigasi I know that such classic grammar description languages need a lot of tweaks and specialcase handlings to work with VHDL, because VHDL is very complex. E.g. it has a very long look-ahead.

Another problem with classic parsers / compilers is that they remove e.g. comments. In my main usecase (documentation extraction) I need these information to match comments to language constructs.

I decided to create a handwritten multi-pass parser that creates several intermediate steps from source file to netlist.

Steps:

1. Create a double linked stream of Token objects.
2. Create a double linked stream of Block objects that group consecutive Tokens
3. Create a double linked stream of hierarchical Groups that group Blocks.
4. Create a CodeDOM (Code Document Object Model) for each single file
5. Merge CodeDOMs to a Language Model (resolve symbols)
6. Create a Netlist:
   • A simulation Netlist that contains only blocks, signals and processes.
   • A synthesis Netlist that transforms VHDL constructs to simpler constructs as describe in the LRM.
7. ...

Back to your question. E.g. pyVHDLParser contains a generic description of VHDL constructs as an Object Model described in Python. Both projects could use such a common model.

E.g. An Entity looks like this:

class Entity(PrimaryUnit):
    def __init__(self):
        super().__init__()
        self._libraryReferences = []
        self._uses =              []
        self._genericItems =      []
        self._portItems =         []
        self._declaredItems =     []
        self._bodyItems =         []

    @property
    def LibraryReferences(self):
        return self._libraryReferences

    @property
    def Uses(self):
        return self._uses

    @property
    def GenericItems(self):
        return self._genericItems

    @property
    def DeclaredItems(self):
        return self._declaredItems

    @property
    def BodyItems(self):
        return self._bodyItems

I don't intend to have a very fast parser (otherwise I would use VB.Net or C# ...), but it should be very flexible so we can test new VHDL features from VHDL-2018 and VHDL-2020 ... :).

In what why would you like to cooperate?

Kind regards Patrick

[Nic30]

Hello,

• I already updated vhdl grammar, it is not an original, which can be found in antrl4 grammar repo.

• Comments are feed to another token stream and hdlConverter currently ignore them.

• HWT/hdlConvertor has similar objects, just parsing/HDL objects are separated from each other https://github.com/Nic30/hdlConvertor/blob/master/src/hdlObjects/context.h https://github.com/Nic30/hwtHdlParsers/blob/master/hwtHdlParsers/hdlObjects/hdlContext.py https://github.com/Nic30/HWToolkit/blob/master/hwt/hdl/entity.py

Since 2015 I had VHDL parser written in python then Cesnet came up with 40MB+ pcie DMA code and I had to use C++. And it is very hard to implement reasonable parser err. reporting/recovery, which is already done in ANTLR4.

I want to cooperate because HDL -> python object conversion is not an easy tasks and it needs to have clean API for others to use.

I would like to keep API of our projects somehow similar. So one day we can share can share some code together.

Currently I do not need hdlConverter, because I already converted all HDL in current company but it may be useful for others.

[Paebbels]

What do you think of an Entity object as described above?

I see, my Entity is missing ContextReferences, while your entity misses:

• declared items and
• statements

Note this is valid VHDL:

entity e is
  generic (
    constant BAR : postive := 16
  );
  port (
    Clock  : in  std_logic;
    Strobe : in  std_logic;
    Done   : out std_logic
  );
  constant FOO : integer := BAR - 1;
begin
  process(Clock)
    variable Delay : natural := 0;
  begin
    if rising_edge(Clock) then
      if (Strobe = '1') then
        Delay := 0;
      else
        Delay := Delay + 1;
      end if;
      assert ((Done = '1') and (Delay = FOO))
        report "Pipeline delay is not correct."
        severity ERROR;
    end if;
  end process;
end entity;

[Nic30]

pyVHDLParser entity has references, hwt entity has context which contains references and another parsed objects in current run, dependencies solved by lazy loading (parse order is dynamically resolved).

pyVHDLParser entity contains body items, hwt architecture contains body items. Process statement/declared components/functions are currently supported only in architecture. (I did not implement this yet because I actually never seen it in real code. But it seems STD is clear about this.)

[Paebbels]

I have seen processes in entities as protocol checkers. I think this was related to OVL - Open Verification Library / Language.

[Nic30]

Ok, I see VHDLModel.py I would like to use this classes as containers for output of my parser as well. But maybe it is too VHDL specific, and not compatible with HDL languages. If we could remove some clasess like Procedure it could be better for other HDL languages.

There is also question if:

• Assert statements can be replaced only by assert function call
• concurrency can be marked only by flag in statement
• generate statements should be preprocessed in preprocessor or converted to regular statements
• dependencies/imports should be solved on context level

(I am not saying that it is VHDL friendly, I just trying to make API more simple and this is my first guess)