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Paebbels / pyVHDLParser

Streaming based VHDL parser.
https://paebbels.github.io/pyVHDLParser/
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Clk'event #4

Open kown7 opened 6 years ago

kown7 commented 6 years ago

The following piece of legal code if Clk'event and Clk = '1' then -- rising clock edge yields this error:

ERROR: Expected ';', ':=' or whitespace after subtype indication.
================================================================================================================================================================
ERROR: (line: 103, col: 12): Ambiguous syntax detected.
Paebbels commented 6 years ago

This project is in development. The pyVHDLParser is not in a stable state yet.

Attributes are not supported yet. (Besides a long list of other features ...)

I should add a hint, that this project is under development :).

kown7 commented 6 years ago

Ignoring them would be very nice though, as I'm more interested in the supported features.

Paebbels commented 3 years ago

Supported features are indirectly visible through the newly added test cases (>250) and the growing documentation at ReadTheDocs.

JC-LL commented 3 years ago

I don't know if it can help. My project "vertigo" : a VHDL parser (93 + many 08 features), written in pure Ruby. https://github.com/JC-LL/vertigo. It parses Microwatt , generates an AST and VHDL back.

Paebbels commented 3 years ago

@JC-LL thanks for pointing to this nice VHDL project. Do you want to try running the PoC Library through your parser? It surfaced a lot of problems in commercial tools :).

What are you using it for?

The goal for pyVHDLParser is generating a CodeDOM and documentation extraction.

Paebbels commented 1 year ago

Fixed by #54.