Open ryan-summers opened 6 years ago
To accomplish this, the reset on the FIFO feeding in to the DMA engine needs to have a control that is operable from the processor. (e.g. AXI GPIO) Then, the firmware could issue a reset to the FIFO before it commands the DMA to save data.
Currently, the DMA engine has an internal buffer of a number of packets. If a period of time goes by where the AXI stream is not read and over runs, future use of the DMA will result in corrupted data left over from before the stream was abandoned. This means that the first few packets received from the DMA engine may potentially be from an arbitrary point in the past.
Add in functionality to the firmware to properly purge the DMA buffers to get rid of stale data.