Block SEQ: Errors in the sequencer block or in application?

[jbeca]

oscilloscope : show errors in sequence.

descripition:

The enable input Blocks are controled by SRGATE1.

The SRGATE 2 and 3 are controlled by the sequencer.

The connections are: SRGATE2.RST=SEQ1.OUTB SRGATE2.SET=SEQ1.OUTA SRGATE3.RST=SEQ1.OUTD SRGATE3.SET=SEQ1.OUTC

The inputs used for the sequencer are:

• a pos input from an encoder (SEQ1.POSA = INENC1.VAL)
• and bit from a rsing edge event come from a ttl input counter SEQ1.BITA = LUT1.OUT LUT1.TYPEA = Pulse-On-Rising-Edge LUT1.INPA=COUNTER8.CARRY COUNTER8.TRIG=TTLIN1.VAL

The sequencer Table: Table line 1,2,3,4 are the sequence base. This sequence are repeted with the table lines (5,6,7,8) and (9,10,11,12).

Erreurs are in sequence ligne 5,8,9,12. (with regard to the reference sequence, there is or not a signal) (There is no signal generated by SEQ to control the srgate2.) (the expected signal is indicated in gray)

Erreurs : The table line 13 is a test "do nothing" but the outputs change. (SEQ does not generate signals to control the srgate, but the srgate2 ant 3 change state)

panda parameters files:

program.txt table.txt

[shu-soleil]

Jerome, could you try to set the SEQ1.TABLE with phase time > 1 (8ns) on each line ?

[thomascobb]

I've reproduced this, I'll look into it...

[shu-soleil]

I've made some short tests yesterday, it seems the SEQ could miss or jump lines when 'Phase 2 Time'=1 (especially lines behind 'immediate' triggered lines?).

[thomascobb]

Yes, the problem is here: https://github.com/PandABlocks/PandABlocks-FPGA/blob/f5798aff4f9b602c450f98e299a8d088e1f82bbb/modules/seq/hdl/seq.vhd#L276-L280

It looks like the last part of the or tries to pre-load in PHASE1 if PHASE2 is too short, but the conditions aren't restrictive enough. I'll try to find a more general fix.

As a workaround, if you make PHASE2 anything other than 1 clock tick then everything seems to work.

[thomascobb]

Tested on a real PandA and it seems to work, so have merged into master