Open thomascobb opened 3 years ago
@tomtrafford do you have time to take a look at this?
Hi @thomascobb Yes I can have a look into this.
Hello, do you think it raisonable to take dma status into account for ACTIVE: ACTIVE=1 until dma finish the transferts then ACTIVE=0 ?
I'm not sure, how much time difference is there typically between then it currently goes low, and when the DMA is complete?
I'm not sure, how much time difference is there typically between then it currently goes low, and when the DMA is complete?
I made some tests, the different could be tens or hundreds of ns, or about 4 ms when the last 2 IRQ are very closed.
And do you have a use case where keeping ACTIVE high an extra 4ms would be useful on the FPGA side? We always wait to do the next scan from when the server sends the completion code to the client, which means the DMA is complete. We use the ACTIVE to gate pulses on the input, so actually I'd prefer to keep the current behaviour of ACTIVE
Add 2 registers to PCAP: