We have a requirement for 50kHz table based position compare. The SEQ block has 4096 rows, and though it is double buffered this would be 11 table writes a second, which gives very little margin for error. Long table support has much bigger buffers, but appending while reading is not currently supported. After discussing the possibilities with @EmilioPeJu and @Araneidae, we think:
The FPGA side of the long table support (reading from a sequence of DMA blocks) seems suitable for this application, but may be lacking some flow control to say when it is ready for the next block
There is a need to run PGEN in a stream mode too, but need to retain the current static mode
If we can make long table support both stream and static mode, then maybe we don't need a short table mode
A possible long term plan is:
Remove short table support and convert SEQ to use long table mode
Remove table append support
Table support (formerly long table support) gains a new MODE attribute that can be fixed or fifo
In fixed mode it does what it currently does
In fifo mode then the value is always empty, clearing of the fifo is done from the FPGA side, and writing to the table will append to the fifo
A plan of how to get there:
Test how fast PGEN can consume the table
Add the MODE attribute to table support on the table, and make writes append to it if in fifo mode
Switch the mode, and run the PGEN test again but make sure the buffers are filled in time
Then add the flow control and clearing to the server and PGEN
coretl
commented
3 weeks ago
We have a requirement for 50kHz table based position compare. The SEQ block has 4096 rows, and though it is double buffered this would be 11 table writes a second, which gives very little margin for error. Long table support has much bigger buffers, but appending while reading is not currently supported. After discussing the possibilities with @EmilioPeJu and @Araneidae, we think:
A possible long term plan is:
MODEattribute that can befixedorfifofixedmode it does what it currently doesfifomode then the value is always empty, clearing of the fifo is done from the FPGA side, and writing to the table will append to the fifoA plan of how to get there:
MODEattribute to table support on the table, and make writes append to it if infifomode