Closed charlespax closed 7 years ago
Here's what I have right now. The unassigned pins would be for the six GPIO pins for the modules. The two SPI_NSS pins plus the six GPIO are the eight GPIO pins required by the interface.
PA10 is unused in this design and is reserved and would be used for USB_OTG if the stm32f412 were used. PB11 is also not used. The stm32f412 uses this pin for a power capacitor. That is also what compelled the decision or use only a single I2C interface.
Board routing looks like it is going to shake out much better.
Out of interest, what did you use to generate those pinout images?
I used STM32CubeMX from ST. It's a super flipping awesome GUI for defining all the pins and peripherals.
It will help define all the timing.
Then it will generate all the startup code in a project. It supports several IDEs. We've been using a secondary Python script to translate from SW4STM32 to and Eclipse project.
Thanks @charlespax. I suspected it was from STMCube. I played with an older version, but only briefly. I have been writing my own startup code so far. Will have to try this latest version out, especially with PCBs for a new design about to land.
Given the following criteria,
The following twenty-seven parts are potentially compatible.
There are a few down sides with taking SDIO as a criteria. The chip with the lowest amount of flash has 128k flash, 64k RAM. That's fine for development, but limits the options for reducing cost in a final product. However, if we were to use a SPI interface instead, we will be compatible with sixty chips. We'd would then only have one SPI interface for all four modules. Not a good trade off.
Here's where I am.
All module GPIO pins are capable of GPIO, external interrupt, and 12-bit ADC measurements. Additional features are carried on the pins as listed below.
I've routed a new board revision. Closing this issue.
One of the nicest aspects of the STM32 family is that the chips are very compatible. If we carefully select the peripheral pin mapping, switching between chips will be relatively trivial.
Here is how pins are mapped in LabWiz v0.2.![screen shot 2016-09-03 at 13 31 35](https://cloud.githubusercontent.com/assets/281642/18222973/c9617cba-71da-11e6-85d1-068d0f01d247.png)
If we change to this pin map, we can swap out the stm32f103rgt (1024k flash, 96k RAM) with the stm32f412rgt (1024k flash,256k RAM).![screen shot 2016-09-03 at 13 29 43](https://cloud.githubusercontent.com/assets/281642/18222967/84e39122-71da-11e6-831f-f9603eee7bd6.png)
Here is the stm32f412.![screen shot 2016-09-03 at 13 30 55](https://cloud.githubusercontent.com/assets/281642/18222982/3fd0cc98-71db-11e6-80eb-84e604077190.png)
The downside of implementing this configuration is that we lose a bit of interface flexibility with the modules. The LabWiz v0.2 design gives two USART, two SPI, and two i2c. The compatibility configuration would give two USART, two SPI, and one i2c. Since i2c is a multi-device bus, this isn't much of an issue.