[DESIGN] - Peltier Driver Circuit

[JLefebvre55]

Completion is tracked in the linked PR.

Design Scope

Design a PWM-dimmable, polarity-switchable driver circuit.

Purpose

The purpose of this driver circuit is to be able to precisely control the heat transfer of a thermoelectric element (Peltier tile).

Function

Inputs:

• DC power
• Control signal (PWM)

Outputs:

• Peltier power

It interfaces with/depends on the following systems:

• Power delivery

Method

There are a number of ways of going about this.

1. All-in-one dimmable current source (aka LED driver) - Pros: Precise power transfer control ($Q$ is proportional to $I$ (source?)); Cons: no models with high enough current output
2. Filtered PWM Voltage Source - Pros: Peltiers are fairly resistive/linear in their load under standard operating conditions, so voltage driving should be fine (source?); Cons: Need to build a f*cking filter circuit, need some kind of feedback system to tell how much current we're actually putting through this thing

We're going to go with option 2. There do not exist any LED drivers with sufficient current output.

Features

Each feature should be added to relevant BoMs and CADs where applicable. Design decisions should be well-supported using relevant research and calculations, and should be documented in the Solution Overview. If a feature is complex enough, create a new issue for it using this template, and tag it here.

In order of connection sequence:

1. Power MOSFET - Generate 0-16V PWM square wave "signal" voltage
2. Low-pass filter - Convert PWM to analog signal (duty cycle -> 0-16V)
3. Voltage buffer (Unity-Gain Op Amp) - Use signal without interfering with filter
4. Amplifier (Darlington) - No current draw from buffer
5. H-bridge - Control polarity

Requirements and Validation

What does this design need to accomplish? How do we know it has accomplished this?

List any applicable metrics with criteria/constraints, applicable to purpose, function, method, and each feature, as well as how to test them.

1. Minimize parasitic/"non-load" power consumption
2. Load power delivery accuracy ±5%

Verification

Each test should be performed and documented, and the testing documentation attached to the PR. The testing suite should address the full scope of the function (i.e. ensure inputs are met and outputs work), method (all steps execute correctly), and features (each feature performs as expected) with respect to the purpose and requirements.

How does this design achieve its method effectively, safely, and reliably? How do we test this?

Specific testing procedure:

1. Test power MOSFET switching and voltage accuracy at load (16±.5V)
2. Test low-pass filter attenuation ripple (PWM% x VCC ±5%) and time constant

[JLefebvre55]

Todo:

• [x] Find peltier voltage requirements 0-16V
• [x] Choose power MOSFET IRLZ44
• [x] Calculate RC values for filter 16kΩ, 1µF (picked for over-attenuation, 10Hz)
• [x] Simulate circuit Here Note: PWM duty cycle should be inverted.
• [x] Choose an op amp LM324
• [x] Choose an NPN Darlington pair 2N6388G, 10A continuous is > 8.5A max current draw from Peltier
• [x] Choose H-bridge Relay
• [ ] Order, assemble and test

Background

Filtering PWM

Note that the primary tradeoff in choosing a cutoff frequency is in attenuation vs time. We are far less concerned with time than with attenuation.

Voltage Buffering for High Current Loads

Op amp current output max is notoriously low. Use a BJT - or better yet, a Darlington - to boost the power. The emitter pin should drive the feedback - this way the base pin "control" voltage outputted from the op amp results in a load voltage equal to the signal voltage.

[JLefebvre55]

Transferred from UofT Agritech repo

[JLefebvre55]

Reopened for testing