draft: Fix how wire mapping is handled by the QuantumComputer device

[MarquessV]

I know we aren't 100% set on the expectations around how we set the wire mapping, but I decided to package this up and document what I understand thus far, so when we do pick it back up, we have some context on where it left off. This PR works against a live QPU in my tests, and all the tests pass (besides a few related to validation of the wires parameter, which is expected).

As I see it, there are two issues to clear up here:

1. What we want users to provide via the wires parameter.

The qml.device documentation states this can be either an integer, in which case qubits are addressed by consecutive integers, or an iterable of the preferred labels.

As of this draft, the PR covers those cases by mapping the labels to Qubits available on the device. This should work well in the general case, as quilc will optimize which qubits are selected based on the device ISA.

One use case that Rigetti power users may miss is being able to specify a subset of qubits on the device based on current performance. As far as I know, there is no established pattern for that kind of specification.

2. How does PennyLane interpret the wire mapping, and how should samples be organized so that readout is mapped correctly between qubits and wires.

I tried to remedy this by:

• Using PennyLanes Wires class to build the same labels it would internally, though this may not be necessary.
• The define_wire_map is inherited from PennyLane's QubitDevice class. It isn't used by this plugin internally, it makes sense conceptually that this would be PennyLane's source of truth for the wire mapping, but I haven't double checked it's source code to see.
• No sorting of the qubits in generate_samples. This is working under the assumption that the order of the generated samples must match the order of what define_wire_map returns.

[sc-54125]

[codecov[bot]]

Codecov Report

All modified and coverable lines are covered by tests :white_check_mark:

:exclamation: No coverage uploaded for pull request base (master@ad74b16). Click here to learn what that means.

Additional details and impacted files

```diff @@ Coverage Diff @@ ## master #147 +/- ## ========================================= Coverage ? 98.47% ========================================= Files ? 10 Lines ? 590 Branches ? 0 ========================================= Hits ? 581 Misses ? 9 Partials ? 0 ```

:umbrella: View full report in Codecov by Sentry.
:loudspeaker: Have feedback on the report? Share it here.

[lillian542]

Made this PR against your branch with a suggested fix. Not sure what else (if anything) it will break, I'm having trouble running the tests locally. But have a look and see what you think: https://github.com/MarquessV/pennylane-forest/pull/2