Open GProtoZeroW opened 6 years ago
This appears to be a problem with the Vivado environment which I've not seen before. Are you able to open Vivado HLS and create a design manually?
Is HLS free, I use myHDL (python library) for my HDL (verilog) generation and then try to play the IP wrapper and block diagram games. Can you send me what TCL commands I need to have my Vivido project sent to you where I am doing the same workflow as the tutorial notebook Because I have had issues with generating the bitstream. Thanks ahead of time for working on some tutorials for the fabric. Any work on lowering the learning curve/barrier to FPGA design work for the PYNQ are going to make it a game changer
HLS is included in the Webpack editions of Vivado so you should have access to it. What error are you getting when building the bitstream?
Finaily Got some time to get back to this Started new HLS project , added the adder to project and specfied it as top cpp file I run the sythn and ~Xilinx/Vivado_HLS/2016.1/include/ap_int.h:74
Could you just extract a Verilog file from HLs synth
Nevermind got it working. I am going to say three things:
Xilinx newbie, but I ran source build_all.tcl and ended up with
Is this just a C HDL thing.
Also in a new overlay build instance once I add the IP I have wrapped my HDL(verilog, ect.) code in to block design can I just throw down a ZYNQ IP block without making any modifications to the ZYNQ IP. And this is assuming that in the vivado project setup I specified the PYNQ-Z1 board files and added the PYNQ-Z1 constraint file.