Closed EmbeddedTec closed 2 years ago
Build scripts works with and bit files are generated successfully (tested with 2020.2 and 2021.2). BUT designs do not work because of a change in Vitis HLS: In versions greater than 2019.2, HLS doesn't generate TLAST signals on AXI Stream busses for the current implementation. Thereby the connection to AXI DMA blocks is broken.
I will adjust the multiplier IP according the HLS stream example from the PYNQ forum: https://discuss.pynq.io/t/tutorial-using-a-hls-stream-ip-with-dma-part-1-hls-design/3344
Thank you very much for the Pull Request. We're in the process of moving the primary repository to https://github.com/schelleg/overlay_tutorial. Would you be able to reissue it there?
I created a pull request on https://github.com/schelleg/overlay_tutorial with the same changes.
Thank you - I'll close this PR
Ported overlays und IP to Vivado/Vitis HLS 2020.2