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PeterOgden / overlay_tutorial

Premade bitstreams and block designs to complemented the PYNQ overlay tutorial
http://pynq.readthedocs.io/en/v2.0/overlay_design_methodology/overlay_tutorial.html
BSD 3-Clause "New" or "Revised" License
38 stars 19 forks source link

Update to 2020.2 and PYNQ v2.7 #4

Closed EmbeddedTec closed 2 years ago

EmbeddedTec commented 2 years ago

Ported overlays und IP to Vivado/Vitis HLS 2020.2

EmbeddedTec commented 2 years ago

Build scripts works with and bit files are generated successfully (tested with 2020.2 and 2021.2). BUT designs do not work because of a change in Vitis HLS: In versions greater than 2019.2, HLS doesn't generate TLAST signals on AXI Stream busses for the current implementation. Thereby the connection to AXI DMA blocks is broken.

I will adjust the multiplier IP according the HLS stream example from the PYNQ forum: https://discuss.pynq.io/t/tutorial-using-a-hls-stream-ip-with-dma-part-1-hls-design/3344

PeterOgden commented 2 years ago

Thank you very much for the Pull Request. We're in the process of moving the primary repository to https://github.com/schelleg/overlay_tutorial. Would you be able to reissue it there?

EmbeddedTec commented 2 years ago

I created a pull request on https://github.com/schelleg/overlay_tutorial with the same changes.

PeterOgden commented 2 years ago

Thank you - I'll close this PR