Stuck on x8

[jl4c]

Hi Pike, am trying to generate a working SSDT with the new version (v12.0) of the script, but it fail because am stuck on x8. Some times ago i generated my SSDT with an old version of the script (v3.6) and with that version my system is working now. Am submit you this issue/bug because i get this same behavior with the following processors: i5-3317U i3-2330m

WORKING SSDT CODE (i5-3317U):

/*

• Intel ACPI Component Architecture
• AML Disassembler version 20130725-64 [Jul 30 2013]
• Copyright (c) 2000 - 2013 Intel Corporation
• Disassembly of iASLfPu9zJ.aml, Sun Feb 23 12:44:25 2014 *
• Original Table Header:
• Signature "SSDT"
• Length 0x0000046F (1135)
• Revision 0x01
• Checksum 0x27
• OEM ID "APPLE "
• OEM Table ID "CpuPm"
• OEM Revision 0x00003000 (12288)
• Compiler ID "INTL"

• Compiler Version 0x20121018 (538054680)

  */ DefinitionBlock ("iASLfPu9zJ.aml", "SSDT", 1, "APPLE ", "CpuPm", 0x00003000) {

  External (PR.CPU0, DeviceObj) External (PR.CPU1, DeviceObj) External (PR.CPU2, DeviceObj) External (PR.CPU3, DeviceObj)

  Store ("ssdtPRGen.sh v3.6", Debug) Store ("baseFrequency : 1200", Debug) Store ("frequency : 1700", Debug) Store ("logicalCPUs : 4", Debug) Store ("tdp : 17", Debug) Store ("packageLength : 15", Debug) Store ("turboStates : 9", Debug) Store ("maxTurboFrequency: 2600", Debug) Scope (_PR.CPU0) { Name (APLF, 0x04) Name (APSN, 0x0A) Name (APSS, Package (0x14) { Package (0x06) { 0x0A29, 0x4268, 0x0A, 0x0A, 0x1B00, 0x1B00 },

    Package (0x06)
    {
        0x0A28, 
        0x4268, 
        0x0A, 
        0x0A, 
        0x1A00, 
        0x1A00
    }, 
  
    Package (0x06)
    {
        0x09C4, 
        0x4268, 
        0x0A, 
        0x0A, 
        0x1900, 
        0x1900
    }, 
  
    Package (0x06)
    {
        0x0960, 
        0x4268, 
        0x0A, 
        0x0A, 
        0x1800, 
        0x1800
    }, 
  
    Package (0x06)
    {
        0x08FC, 
        0x4268, 
        0x0A, 
        0x0A, 
        0x1700, 
        0x1700
    }, 
  
    Package (0x06)
    {
        0x0898, 
        0x4268, 
        0x0A, 
        0x0A, 
        0x1600, 
        0x1600
    }, 
  
    Package (0x06)
    {
        0x0834, 
        0x4268, 
        0x0A, 
        0x0A, 
        0x1500, 
        0x1500
    }, 
  
    Package (0x06)
    {
        0x07D0, 
        0x4268, 
        0x0A, 
        0x0A, 
        0x1400, 
        0x1400
    }, 
  
    Package (0x06)
    {
        0x076C, 
        0x4268, 
        0x0A, 
        0x0A, 
        0x1300, 
        0x1300
    }, 
  
    Package (0x06)
    {
        0x0708, 
        0x4268, 
        0x0A, 
        0x0A, 
        0x1200, 
        0x1200
    }, 
  
    Package (0x06)
    {
        0x06A4, 
        0x4268, 
        0x0A, 
        0x0A, 
        0x1100, 
        0x1100
    }, 
  
    Package (0x06)
    {
        0x0640, 
        0x3DCA, 
        0x0A, 
        0x0A, 
        0x1000, 
        0x1000
    }, 
  
    Package (0x06)
    {
        0x05DC, 
        0x3944, 
        0x0A, 
        0x0A, 
        0x0F00, 
        0x0F00
    }, 
  
    Package (0x06)
    {
        0x0578, 
        0x34D6, 
        0x0A, 
        0x0A, 
        0x0E00, 
        0x0E00
    }, 
  
    Package (0x06)
    {
        0x0514, 
        0x307F, 
        0x0A, 
        0x0A, 
        0x0D00, 
        0x0D00
    }, 
  
    Package (0x06)
    {
        0x04B0, 
        0x2C3F, 
        0x0A, 
        0x0A, 
        0x0C00, 
        0x0C00
    }, 
  
    Package (0x06)
    {
        0x044C, 
        Zero, 
        0x0A, 
        0x0A, 
        0x0B00, 
        0x0B00
    }, 
  
    Package (0x06)
    {
        0x03E8, 
        Zero, 
        0x0A, 
        0x0A, 
        0x0A00, 
        0x0A00
    }, 
  
    Package (0x06)
    {
        0x0384, 
        Zero, 
        0x0A, 
        0x0A, 
        0x0900, 
        0x0900
    }, 
  
    Package (0x06)
    {
        0x0320, 
        Zero, 
        0x0A, 
        0x0A, 
        0x0800, 
        0x0800
    }
  })
  Method (ACST, 0, NotSerialized)
  {
    Store ("CPU0 C-States    : 29", Debug)
    Return (Package (0x06)
    {
        One, 
        0x04, 
        Package (0x04)
        {
            ResourceTemplate ()
            {
                Register (FFixedHW, 
                    0x01,               // Bit Width
                    0x02,               // Bit Offset
                    0x0000000000000000, // Address
                    0x01,               // Access Size
                    )
            }, 
  
            One, 
            Zero, 
            0x03E8
        }, 
  
        Package (0x04)
        {
            ResourceTemplate ()
            {
                Register (FFixedHW, 
                    0x01,               // Bit Width
                    0x02,               // Bit Offset
                    0x0000000000000010, // Address
                    0x03,               // Access Size
                    )
            }, 
  
            0x03, 
            0xCD, 
            0x01F4
        }, 
  
        Package (0x04)
        {
            ResourceTemplate ()
            {
                Register (FFixedHW, 
                    0x01,               // Bit Width
                    0x02,               // Bit Offset
                    0x0000000000000020, // Address
                    0x03,               // Access Size
                    )
            }, 
  
            0x06, 
            0xF5, 
            0x015E
        }, 
  
        Package (0x04)
        {
            ResourceTemplate ()
            {
                Register (FFixedHW, 
                    0x01,               // Bit Width
                    0x02,               // Bit Offset
                    0x0000000000000030, // Address
                    0x03,               // Access Size
                    )
            }, 
  
            0x07, 
            0xF5, 
            0xC8
        }
    })
  }
  
  Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
  {
    If (LEqual (Arg2, Zero))
    {
        Return (Buffer (One)
        {
             0x03
        })
    }
  
    Return (Package (0x02)
    {
        "plugin-type", 
        One
    })
  }

  }

  Scope (_PR.CPU1) { Method (APSS, 0, NotSerialized) { Return (_PR.CPU0.APSS) }

  Method (ACST, 0, NotSerialized)
  {
    Store ("CPU1 C-States    : 7", Debug)
    Return (Package (0x05)
    {
        One, 
        0x03, 
        Package (0x04)
        {
            ResourceTemplate ()
            {
                Register (FFixedHW, 
                    0x01,               // Bit Width
                    0x02,               // Bit Offset
                    0x0000000000000000, // Address
                    0x01,               // Access Size
                    )
            }, 
  
            One, 
            0x03E8, 
            0x03E8
        }, 
  
        Package (0x04)
        {
            ResourceTemplate ()
            {
                Register (FFixedHW, 
                    0x01,               // Bit Width
                    0x02,               // Bit Offset
                    0x0000000000000010, // Address
                    0x03,               // Access Size
                    )
            }, 
  
            0x02, 
            0x94, 
            0x01F4
        }, 
  
        Package (0x04)
        {
            ResourceTemplate ()
            {
                Register (FFixedHW, 
                    0x01,               // Bit Width
                    0x02,               // Bit Offset
                    0x0000000000000030, // Address
                    0x03,               // Access Size
                    )
            }, 
  
            0x03, 
            0xC6, 
            0xC8
        }
    })
  }

  }

  Scope (_PR.CPU2) { Method (APSS, 0, NotSerialized) { Return (_PR.CPU0.APSS) }

  Method (ACST, 0, NotSerialized)
  {
    Return (\_PR.CPU1.ACST ())
  }

  }

  Scope (_PR.CPU3) { Method (APSS, 0, NotSerialized) { Return (_PR.CPU0.APSS) }

  Method (ACST, 0, NotSerialized)
  {
    Return (\_PR.CPU1.ACST ())
  }

  } }

DON'T WORKING SSDT CODE (i5-3317U):

/*

• Intel ACPI Component Architecture
• AML Disassembler version 20130725-64 [Jul 30 2013]
• Copyright (c) 2000 - 2013 Intel Corporation
• Disassembly of iASLZihFeu.aml, Sun Feb 23 12:47:05 2014 *
• Original Table Header:
• Signature "SSDT"
• Length 0x000005BC (1468)
• Revision 0x01
• Checksum 0x28
• OEM ID "APPLE "
• OEM Table ID "CpuPm"
• OEM Revision 0x00012000 (73728)
• Compiler ID "INTL"

• Compiler Version 0x20130117 (538116375)

  */ DefinitionBlock ("iASLZihFeu.aml", "SSDT", 1, "APPLE ", "CpuPm", 0x00012000) {

  External (PR.CPU0, DeviceObj) External (PR.CPU1, DeviceObj) External (PR.CPU2, DeviceObj) External (PR.CPU3, DeviceObj)

  Scope (_PR.CPU0) { Method (_INI, 0, NotSerialized) // _INI: Initialize { Store ("ssdtPRGen version....: 12.0 / Mac OS X 10.9.1 (13B42)", Debug) Store ("target processor.....: i5-3317U", Debug) Store ("running processor....: Intel(R) Core(TM) i5-3317U CPU @ 1.70GHz", Debug) Store ("baseFrequency........: 1200", Debug) Store ("frequency............: 1700", Debug) Store ("busFrequency.........: 100", Debug) Store ("logicalCPUs..........: 4", Debug) Store ("maximum TDP..........: 17", Debug) Store ("packageLength........: 15", Debug) Store ("turboStates..........: 9", Debug) Store ("maxTurboFrequency....: 2600", Debug) Store ("machdep.xcpm.mode....: 0", Debug) }

  Name (APLF, Zero)
  Name (APSN, 0x09)
  Name (APSS, Package (0x0F)
  {
    Package (0x06)
    {
        0x0A28, 
        0x4268, 
        0x0A, 
        0x0A, 
        0x1A00, 
        0x1A00
    }, 
  
    Package (0x06)
    {
        0x09C4, 
        0x4268, 
        0x0A, 
        0x0A, 
        0x1900, 
        0x1900
    }, 
  
    Package (0x06)
    {
        0x0960, 
        0x4268, 
        0x0A, 
        0x0A, 
        0x1800, 
        0x1800
    }, 
  
    Package (0x06)
    {
        0x08FC, 
        0x4268, 
        0x0A, 
        0x0A, 
        0x1700, 
        0x1700
    }, 
  
    Package (0x06)
    {
        0x0898, 
        0x4268, 
        0x0A, 
        0x0A, 
        0x1600, 
        0x1600
    }, 
  
    Package (0x06)
    {
        0x0834, 
        0x4268, 
        0x0A, 
        0x0A, 
        0x1500, 
        0x1500
    }, 
  
    Package (0x06)
    {
        0x07D0, 
        0x4268, 
        0x0A, 
        0x0A, 
        0x1400, 
        0x1400
    }, 
  
    Package (0x06)
    {
        0x076C, 
        0x4268, 
        0x0A, 
        0x0A, 
        0x1300, 
        0x1300
    }, 
  
    Package (0x06)
    {
        0x0708, 
        0x4268, 
        0x0A, 
        0x0A, 
        0x1200, 
        0x1200
    }, 
  
    Package (0x06)
    {
        0x06A4, 
        0x4268, 
        0x0A, 
        0x0A, 
        0x1100, 
        0x1100
    }, 
  
    Package (0x06)
    {
        0x0640, 
        0x3DCA, 
        0x0A, 
        0x0A, 
        0x1000, 
        0x1000
    }, 
  
    Package (0x06)
    {
        0x05DC, 
        0x3944, 
        0x0A, 
        0x0A, 
        0x0F00, 
        0x0F00
    }, 
  
    Package (0x06)
    {
        0x0578, 
        0x34D6, 
        0x0A, 
        0x0A, 
        0x0E00, 
        0x0E00
    }, 
  
    Package (0x06)
    {
        0x0514, 
        0x307F, 
        0x0A, 
        0x0A, 
        0x0D00, 
        0x0D00
    }, 
  
    Package (0x06)
    {
        0x04B0, 
        0x2C3F, 
        0x0A, 
        0x0A, 
        0x0C00, 
        0x0C00
    }
  })
  Method (ACST, 0, NotSerialized)
  {
    Store ("Method CPU0.ACST Called", Debug)
    Store ("CPU0 C-States    : 29", Debug)
    Return (Package (0x06)
    {
        One, 
        0x04, 
        Package (0x04)
        {
            ResourceTemplate ()
            {
                Register (FFixedHW, 
                    0x01,               // Bit Width
                    0x02,               // Bit Offset
                    0x0000000000000000, // Address
                    0x01,               // Access Size
                    )
            }, 
  
            One, 
            Zero, 
            0x03E8
        }, 
  
        Package (0x04)
        {
            ResourceTemplate ()
            {
                Register (FFixedHW, 
                    0x01,               // Bit Width
                    0x02,               // Bit Offset
                    0x0000000000000010, // Address
                    0x03,               // Access Size
                    )
            }, 
  
            0x03, 
            0xCD, 
            0x01F4
        }, 
  
        Package (0x04)
        {
            ResourceTemplate ()
            {
                Register (FFixedHW, 
                    0x01,               // Bit Width
                    0x02,               // Bit Offset
                    0x0000000000000020, // Address
                    0x03,               // Access Size
                    )
            }, 
  
            0x06, 
            0xF5, 
            0x015E
        }, 
  
        Package (0x04)
        {
            ResourceTemplate ()
            {
                Register (FFixedHW, 
                    0x01,               // Bit Width
                    0x02,               // Bit Offset
                    0x0000000000000030, // Address
                    0x03,               // Access Size
                    )
            }, 
  
            0x07, 
            0xF5, 
            0xC8
        }
    })
  }
  
  Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
  {
    Store ("Method CPU0._DSM Called", Debug)
    If (LEqual (Arg2, Zero))
    {
        Return (Buffer (One)
        {
             0x03
        })
    }
  
    Return (Package (0x02)
    {
        "plugin-type", 
        One
    })
  }

  }

  Scope (_PR.CPU1) { Method (APSS, 0, NotSerialized) { Store ("Method PR.CPU1.APSS Called", Debug) Return (_PR.CPU0.APSS) }

  Method (ACST, 0, NotSerialized)
  {
    Store ("Method CPU1.ACST Called", Debug)
    Store ("CPU1 C-States    : 7", Debug)
    Return (Package (0x05)
    {
        One, 
        0x03, 
        Package (0x04)
        {
            ResourceTemplate ()
            {
                Register (FFixedHW, 
                    0x01,               // Bit Width
                    0x02,               // Bit Offset
                    0x0000000000000000, // Address
                    0x01,               // Access Size
                    )
            }, 
  
            One, 
            0x03E8, 
            0x03E8
        }, 
  
        Package (0x04)
        {
            ResourceTemplate ()
            {
                Register (FFixedHW, 
                    0x01,               // Bit Width
                    0x02,               // Bit Offset
                    0x0000000000000010, // Address
                    0x03,               // Access Size
                    )
            }, 
  
            0x02, 
            0x94, 
            0x01F4
        }, 
  
        Package (0x04)
        {
            ResourceTemplate ()
            {
                Register (FFixedHW, 
                    0x01,               // Bit Width
                    0x02,               // Bit Offset
                    0x0000000000000030, // Address
                    0x03,               // Access Size
                    )
            }, 
  
            0x03, 
            0xC6, 
            0xC8
        }
    })
  }

  }

  Scope (_PR.CPU2) { Method (APSS, 0, NotSerialized) { Store ("Method PR.CPU2.APSS Called", Debug) Return (_PR.CPU0.APSS) }

  Method (ACST, 0, NotSerialized)
  {
    Return (\_PR.CPU1.ACST ())
  }

  }

  Scope (_PR.CPU3) { Method (APSS, 0, NotSerialized) { Store ("Method PR.CPU3.APSS Called", Debug) Return (_PR.CPU0.APSS) }

  Method (ACST, 0, NotSerialized)
  {
    Return (\_PR.CPU1.ACST ())
  }

  } }

[Piker-Alpha]

Hi,

Well. That seems like a step backwards doesn't it. Trust me. I don't like it either, but as a work around. For the time being. Use the -w script argument if you want to use AppleIntelCPUPowerManagement.kext i.e. start the script with: ./ssdtPRGen.sh -w 3 because that should work. Don't use -w 3 when you use/want to use XCPM (Apple's own mach_kernel PM implementation). And yes. I'll try to figure out a way to automate this step also.

Thank you for reporting this bug here!