How to organize scheduled and unscheduled buffer on TOR？

[Bajie-cigarette]

Hi behnamm.I read your paper and I wonder some details of Homa. How to organize scheduled and unscheduled buffer in TOR? Is TOR a output-buffered router? I think TOR must not be a input-buffered router. If so, only one Flit will output though output port each cycle, and the Flit couldn't be buffered because it will arrive Receiver and been retired immediately.

[behnamm]

Hi @Bajie-cigarette

Could you explain what you mean by "organize scheduled and unscheduled"? The switch model is output queue, priority forwarded switch. Check out slides 13 and 14 of the SIGCOMM presentation of Homa for a schematic that shows how packets are ordered and priority buffered at the TOR port to the receiver host. You can download the slides here: https://conferences.sigcomm.org/sigcomm/2018/program_wednesday.html

Basically, each receiver host has a link to a an egress port on TOR switch. The egress ports can buffer packets at the output and priority forward them the receiver. Each packet at the time of transmission at the sender is tagged by priority level in the packet header and the switch arbiter/classifier orders the packets at the TOR's egress port based on that priority level.

[Bajie-cigarette]

Thanks for your reply! I'm sorry for my poor English, hhh…… The question I wanted to asked is: Is the switch input-queued or output-queued? OK, you had told me that the TOR is output-queued. So is there input buffer in the TOR? How could the output buffer receive multi Flits each cycle?

[behnamm]

I do not have experience in hardware and ASICs designs of the switches. All I can say is that Homa doesn't depend on any specialized hardware feature from switches and doesn't add any thing new to the switch ASIC design.

To best of my knowledge, today's commodity switches that are being used in datacenter networks, can be abstractly modeled as virtual output queue switches that can support up to 8 priority queues per output port. And, that's all Homa assumes about the network switch; nothing more!

The question that how the switch ASIC is implemented and if there are any input buffers in the switch or not, I don't know how to answer. There might be input buffers involved in the switch ASIC pipeline, but we trust that we can model the switch as virtual output queue switches.

[Bajie-cigarette]

Thanks a lot~

[Bajie-cigarette]

Hi, behnamm! I am sorry to bother you again. I wonder if only the TOR switches are output-queued, or all the switches in network are output-queued?