Open Preethiaralikatti opened 8 months ago
Introduction to RISC V
From Software Applications to Hardware
SoC Design and OpenLANE
Simplified RTL to GDS flow
Introduction to OpenLANE and Strive Chipsets
Introduction to OpenLANE detailed ASIC Design Flow
Get Familiar to Opensource EDA tools
Design Preparation Step
Review Files After Design Prep and Run Synthesis
/home/vsduser/Pictures/Screenshot from 2024-03-26 20-00-11.png Steps to charecterise Synthesis results
Introduction to QFN