Open zhanghongce opened 5 years ago
Current ILA verification target generation only supports Verilog. The automation part needs analysis of Verilog to create a well-formed wrapper. Some suggestions to the possible System Verilog parser we can use:
https://j.mp/openeda-diagram
Current ILA verification target generation only supports Verilog. The automation part needs analysis of Verilog to create a well-formed wrapper. Some suggestions to the possible System Verilog parser we can use:
https://j.mp/openeda-diagram