Verilog Modifier Improvement & etc.

[zhanghongce]

improve:

• vlg_mod: better way to find the right place to add wires to the module

fix:

• verilog_gen's test: now will free ast after the parsing test
• single_target: missing uf_constraint

[zhanghongce]

Previous PR error seems to be due to service glitch on the CI server.

* pass in manual re-run.

Thanks!