Verilog analysis build fail under release mode

[Bo-Yuan-Huang]

Describe the bug Build fail under Release model.

To Reproduce Steps to reproduce the behavior:

1. cmake .. -DCMAKE_BUILD_TYPE=Release
2. make
3. See error

Expected behavior

ILAng/src/verilog-in/verilog_analysis.cc: In member function ‘void ilang::VerilogAnalyzer::check_resolve_modules(verilog_source_tree*)’:
ILAng/src/verilog-in/verilog_analysis.cc:135:68: error: invalid use of void expression
    PrintMetaAst(ILA_ERROR << "Redeclaration of module @", module) 

ILAng/src/verilog-in/verilog_analysis.cc: In member function ‘ilang::VerilogAnalyzer::hierarchical_name_type ilang::VerilogAnalyzer::_check_hierarchical_name_type(const string&) const’:
ILAng/src/verilog-in/verilog_analysis.cc:355:35: error: invalid use of void expression port_id_ptr); 
ILAng/src/verilog-in/verilog_analysis.cc:380:34: error: invalid use of void expression reg_decl_ptr);
ILAng/src/verilog-in/verilog_analysis.cc:404:34: error: invalid use of void expression net_decl_ptr);

Environment (please complete the following information):

• OS: Ubuntu 16.04
• Compiler [e.g. gcc 5.4.0]