add new module

[buddynohair]

Hello, i want to add a custom verilog module, but there's no tutorial showing me how to do that. can you give me some advice?

[angl-dev]

Hi @buddynohair , sorry that the tutorial is still under development. In the mean time, I'd suggest you check this out:

https://github.com/PrincetonUniversity/prga.py/blob/master/prga/cfg/scanchain/lib.py#L291

This method showcases the creation of various basic or multi-modal primitives. It might take a while to fully understand everything here though, because it involves adding your own Verilog template, adding extra commands to the Yosys synthesis script, and adding attributes related to the specific configuration circuitry and VTR.

[buddynohair]

Hi, ok i think its little bit complicated. And i have another question, if its possible to generate a DSP-Block?

[angl-dev]

Hi @buddynohair , Yes, but currently there's no built-in design for the DSP-block. However, I'd be glad to help if you want to add one. It won't be very complex if you don't need to make it multi-modal, and you don't need to add Yosys commands if inference is not needed.

[buddynohair]

Hi, Yes, im very glad to do it. I also wanna put a LUT in the DSP-Block. Sorry, currently i don't have any idea how to add the DSP_Block. Would you mind telling something about it ?

Ang Li notifications@github.com 于2020年9月12日周六 上午7:44写道：

Hi @buddynohair https://github.com/buddynohair , Yes, but currently there's no built-in design for the DSP-block. However, I'd be glad to help if you want to add one. It won't be very complex if you don't need to make it multi-modal, and you don't need to add Yosys commands if inference is not needed.

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[angl-dev]

@buddynohair sure. For single-mode DSP, you can do the following:

from prga.netlist.net.util import NetUtils

dsp = ctx.build_primitive("dsp")
clk = dsp.create_clock("clk")
A= dsp.create_input("A", 32, clock = "clk")
B = dsp.create_input("B", 32, clock = "clk")
C = dsp.create_output("C", 64, clock = "clk")
NetUtils.connect(clk, [A, B, C], fully = True)

dsp = dsp.build_logical_counterpart(verilog_template = "/absolute/path/to/dsp.v").commit()

Then you can instantiate dsp in the same way as LUTs, flipflops or so.

Note the you are expected to provide the Verilog file, and the port definitions should match the interface of the Verilog file. The NetUtils.connect call at the end marks port A, B, and C as sequential startpoints/endpoints, correspondingly.

[buddynohair]

Hello, i have serval questions. I should add the code you have given in the build.py file or? And is it the way to generate a DSP-Block? Sorry, i thought it more likes to generate a [custom module]. But i wanna get a new [block] actually.

[angl-dev]

Hi @buddynohair , yes you should add these in the build.py file, and indeed it generates a [module] (more accurately a [primitive]), not a [block]. To create a block for the DSP module, you can refer to this example which creates a block for a SRAM module:

https://github.com/PrincetonUniversity/prga/blob/release/examples/fpga/pktchain/fle6_N6_mem8K_42x34/build.py#L48

[buddynohair]

Hi, as you can see, i defined a new module called mux8to1 in the build.py file. But i didn't understand why this error comes out. Compared with yours, i don't define a clock, because its not necessary for a multiplexer. Does it cause the error and it means, only the sequential circuit module is supported?

[angl-dev]

Hi @buddynohair it's a syntax error for the NetUtils.connect method. I think what you mean is NetUtils.connect( [sel, data_in], out, fully = True). The first argument is sources, and the second is for sinks, then use keyword-indxed argument fully to make crossbar connection insteads of bitwise connections.

[buddynohair]

Hi, sorry for the disturb again. The FPGA is successfully built, but there's an error in the implementation step. I can't figure out why. I kinda write the dsp-block and the dsptile in the similar way as your bram in the tutorial

can you please give me a suggestion?

[angl-dev]

Hi @buddynohair sorry I can read German (is this German?) so I have no idea what is happenning here. It looks like you don't have Synopsys VCS installed though..

[buddynohair]

Hi, yes it show VCS command not found. ***[Makefile.sim:227: sim_bcd2bin] Error 127. But it's pretty wired, i tried it with the tiny_k4_N4 and it worked.

[angl-dev]

hi @buddynohair that makes sense. tiny_k4_N4 by default uses iverilog instead of vcs. you can see that if you check the Makefile corresponding to that example. typically we run vcs for large designs. it is faster, and also handles special cases better (e.g. oscillation loops, delta time updates, etc.) we currently don't have native support for modelsim or other commercial simulators.

[buddynohair]

Hi, then i tried the dsptile with the tiny_k4_N4 and everything ran successfully. But the dsptile isn't generated in the rtl folder. What could be the problem? build.zip

[angl-dev]

Hi @buddynohair where did you put your dsptile RTL? (you need to write your own RTL for custom modules) Currently in the release branch, custom Verilog file/templates are not supported in a user-friendly way, so I actually suggest you copy your own Verilog over to the directory after RTL generation. The custom Verilog support will be smoother in the next release.

[buddynohair]

Hello, maybe you misunderstand what i mean. I actually did this : in the k4_N4 build.py, i wrote a new custom block, tile named dsp just like your bram, and in this dsp block i defined a module named mux8to1. But the problem is, i can't find the dsp is integrated, what means there's no Verilog output for the dsp block and tile. Do you understand what i mean ?

In the first screenshot you can see the bram.v and the bram.tile are generated. But in the second one, although i wrote the dsp block and tile, there's nothing for it

[angl-dev]

Hi @buddynohair I see. Did you instantiate that block in any arrays? You can search in build.py and see how the memory blocks are instantiated (e.g. https://github.com/PrincetonUniversity/prga/blob/release/examples/fpga/tiny/fle6_N2_mem8K_8x8/build.py#L60). Then you can instantiate your DSP blocks/tiles similarly. PRGA only generates files when the modules are actually used in your FPGA.

[buddynohair]

Hi, would you please have a look on this , i don't see any difference between mein and yours

[angl-dev]

Hi @buddynohair I think the problem is when you instantiate dsptile in subarray, you only instantiate dsptile when x == 4 && y % 2 ==0. However, since subarray is only 4x4, this condition is never met. Could you try this instead:

for x, y in product(range(4), range(4)):
    if x == 1:
        if y % 2 == 0:
            builder.instantiate(dsptile, (x, y))
    elif x == 2:
        pass # dsptile is 2x2
    else:
        builder.instantiate(clbtile, (x, y))

[buddynohair]

Hi, really sorry. Im sure i give the right absolute path. And because of this error, the rtl.filder isn't successfully generated so i can't add this mux8to1.v after the rtf generation

[angl-dev]

Hi @buddynohair no worries. This is not your fault, and it is a known issue on the release branch. A temporary solution is, you can put your mux8to1 Verilog source file in prga.py/prga/renderer/templates, then use the file name (not the absolute or relative path) as the verilog_template.

An update on the release branch is scheduled probrably for next month. There will be a few minor changes to the API syntax, and the support for custom Verilog will be better.

Plus, is this mux8to1 configurable?

[buddynohair]

Thank you very much!!! I finally solved it.

[angl-dev]

Hi @buddynohair awesome! Just let me know if you have other questions.

Actually, I'd suggest you take a look at the synthesis log, or the synthesized netlist ({design}.blif) to make sure mux8to1 is actually used. I feel sorry to say it, but it's highly possible that your custom module is not actually used in the synthesized netlist. This module will only be actually used if: 1) it is directly instantiated in your target Verilog (e.g. bcd2bin.v), and you add it as a blackbox in your Yosys script; 2) you add a techmap script in Yosys, so that Yosys can synthesize logic onto it. This is another topic though, so if you need help on those, you can create a new issue.

[buddynohair]

Hi, i just checked the route.log and i think you are right ........ the dsptile isn't used......

[angl-dev]

Yeah.. So here are my suggestions:

1. Check in your output directory: syn/syn.ys and see if there is a line like this: read_verilog -lib mux8to1.v. If not, you need to refer to http://www.clifford.at/yosys/cmd_read_verilog.html and add this line at the top of syn.ys
2. In your target application, e.g. bcd2bin.v, directly instantiate mux8to1 as a submodule and make up some logic around them.
3. Rerun the flow. In this way, Yosys should use mux8to1 as a blackbox and output it in the synthesized netlist (bcd2bin.blif), and VPR should be able to place and route it.

[angl-dev]

If you want Yosys to infer mux8to1, e.g. in your target application you have a case statement and you want Yosys to use mux8to1 when possible, you'll need to write a techmap script( doc, example ). You'll also need to register this techmap script into the PRGA generation flow like this.

[buddynohair]

Hello, thanks for the suggestion, but i think its pretty hard to write the mux8to1 as a submodule of a FSDM...

Ang Li notifications@github.com 于2020年9月17日周四 上午6:22写道：

If you want Yosys to infer mux8to1, e.g. in your target application you have a case statement and you want Yosys to use mux8to1 when possible, you'll need to write a techmap script( doc http://www.clifford.at/yosys/cmd_techmap.html, example https://github.com/PrincetonUniversity/prga.py/blob/42806233b7090ff8a2b8dc84995db826f0c91f03/prga/cfg/scanchain/templates/adder.techmap.tmpl.v ). You'll also need to register this techmap script into the PRGA generation flow like this https://github.com/PrincetonUniversity/prga.py/blob/42806233b7090ff8a2b8dc84995db826f0c91f03/prga/cfg/scanchain/lib.py#L372 .

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[angl-dev]

Hi @buddynohair then in what scenario do you expect mux8to1 to be used? You can design anything that contains mux8to1 and use that.

This is a pretty generic problem in synthesis.. The synthesis tool cannot just imagine what function your module does and magically implement logic with your module..

[buddynohair]

Hi, actually i just wanna try out if the prga flow works with the new block. The bcd2bin module is already with input, output and logic description defined, can i just write some new inputs, outputs and logic description in the bcd2bin module and combine them with the mux8to1 sub.module?

Ang Li notifications@github.com 于2020年9月17日周四 下午5:52写道：

Hi @buddynohair https://github.com/buddynohair then in what scenario do you expect mux8to1 to be used? You can design anything that contains mux8to1 and use that.

This is a pretty generic problem in synthesis.. The synthesis tool cannot just imagine what function your module does and magically implement logic with your module..

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[angl-dev]

Hi @buddynohair yeah you can modify bcd2bin.v for your purpose. Just make sure you make corresponding changes in bcd2bin_host.v as well. If you don't want to actually test your design, you can simply add the input ports of bcd2bin as output ports in bcd2bin_host and tie them to constant values, and add the output ports of bcd2bin as input ports in bcd2bin_host and leave them unused.

In the future we'll have another tool alongside simproj to generate a full CAD flow script without requiring the testbench.

[buddynohair]

Hi, sorry, can you please help me more xD. I kinda add the new input and output in the bcd2bin module and combine it with the mux8to1. But an error shows no top_module is specified , although i think i do it in the screenshot2? [image: 截屏2020-09-18上午11.59.33.png] [image: 截屏2020-09-18上午11.59.46.png]

Ang Li notifications@github.com 于2020年9月18日周五 上午12:06写道：

Hi @buddynohair https://github.com/buddynohair yeah you can modify bcd2bin.v for your purpose. Just make sure you make corresponding changes in bcd2bin_host.v as well. If you don't want to actually test your design, you can simply add the input ports of bcd2bin as output ports in bcd2bin_host and tie them to constant values, and add the output ports of bcd2bin as input ports in bcd2bin_host and leave them unused.

In the future we'll have another tool alongside simproj to generate a full CAD flow script without requiring the testbench.

— You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub https://github.com/PrincetonUniversity/prga/issues/10#issuecomment-694524458, or unsubscribe https://github.com/notifications/unsubscribe-auth/AP6XRE5D3ZTQXPIIDHQ5AHTSGKCAFANCNFSM4QRRGYJA .

[angl-dev]

Hi @buddynohair no worries, I can help you, but I can't see your screenshots. You can fork this project, commit your changes and I can take a look into your changes.

[angl-dev]

Resolved with PR #12 .