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PrincetonUniversity / prga

Open-source FPGA research and prototyping framework.
http://parallel.princeton.edu/prga/
BSD 3-Clause "New" or "Revised" License
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new blocks and bitstream #11

Closed buddynohair closed 4 years ago

buddynohair commented 4 years ago

Hello,

i try to generate a new custom block called "hard_logic_block" (similar as a DSP-block), which has the same level as club-block from the hierarchy , but it shows me an error.

截屏2020-09-06下午11 18 51 截屏2020-09-06下午11 19 11

Besides, i still wanna ask something about Bitstream. I think the FPGA is successfully generated, but i can't find the bitstream file in the output files.

angl-dev commented 4 years ago

Hi @buddynohair , for the first question, I think you're missing a closing parenthesis at the end of the if condition.

As for bitstream file, if you are able to run the simulation and get the test passed message, you should find the bitstream file: examples/target/{design}/{fpga}/{design}.memh.

buddynohair commented 4 years ago

Hallo,

Thank you very much, i have found it.

Ang Li notifications@github.com 于2020年9月8日周二 上午8:33写道：

Hi @buddynohair https://github.com/buddynohair , for the first question, I think you're missing a closing parenthesis at the end of the if condition.

As for bitstream file, if you are able to run the simulation and get the test passed message, you should find the bitstream file: examples/target/{design}/{fpga}/{design}.memh.

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