naeimiali7 commented 4 years ago

I got your source code from here and install all modules "YOYS, VTR, PRGA" without any error, and done all the process which indicated in the documentation.

cd /path/to/prga/
./envscr/install

then I built an FPGA "tiny/k4/N2_8x8" without any error, but during implementation and simulation I got the following error :

Could anyone help me solve this issue?

Thanks in advance.

Ubuntu 20.04.1 LTS 5.4.0-48-generic
GNU Make 4.2.1
Clang version 10.0.0-4ubuntu1
Python 3.8.2

gcc version 9.3.0

# Re-activate virtual environment if you exited or started a new terminal session
#   cd /path/to/prga/                           # cd to the root
#   ./envscr/activate                           # activate the virtual environment
cd examples/target/bcd2bin/tiny_k4_N2_8x8   # choose one design and one FPGA
make                                        # run all the way to verification

Output of make :


make -f Makefile.sim
make[1]: Entering directory '/home/john/work/python/john/prga/examples/target/bcd2bin/tiny_k4_N2_8x8'
vpr /home/john/work/python/john/prga/examples/fpga/tiny/k4_N2_8x8/vpr/arch.xml bcd2bin.blif --circuit_format eblif --pack --net_file bcd2bin.net --constant_net_method route \
| tee bcd2bin.pack.log
VPR FPGA Placement and Routing.
Version: 8.1.0-dev+2c288b884
Revision: v8.0.0-2839-g2c288b884
Compiled: 2020-09-24T13:25:10
Compiler: GNU 9.3.0 on Linux-5.4.0-48-generic x86_64
Build Info: release IPO VTR_ASSERT_LEVEL=2

University of Toronto verilogtorouting.org vtr-users@googlegroups.com This is free open source code under MIT license.

VPR was run with the following command-line: vpr /home/john/work/python/john/prga/examples/fpga/tiny/k4_N2_8x8/vpr/arch.xml bcd2bin.blif --circuit_format eblif --pack --net_file bcd2bin.net --constant_net_method route

Architecture file: /home/john/work/python/john/prga/examples/fpga/tiny/k4_N2_8x8/vpr/arch.xml Circuit name: bcd2bin

Loading Architecture Description

Loading Architecture Description took 0.00 seconds (max_rss 14.2 MiB, delta_rss +0.0 MiB)

Building complex block graph

Building complex block graph took 0.00 seconds (max_rss 14.2 MiB, delta_rss +0.0 MiB)

Error 1: Type: Blif file File: bcd2bin.blif Line: 158 Message: Failed to find matching architecture model for '$_SDFFPP0'

Load circuit

Found constant-zero generator '$false' Found constant-one generator '$true' Found constant-zero generator '$undef'

Load circuit took 0.00 seconds (max_rss 16.1 MiB, delta_rss +1.9 MiB)

The entire flow of VPR took 0.00 seconds (max_rss 16.1 MiB) make[1]: [Makefile.sim:201: bcd2bin.net] Error 1 make[1]: Leaving directory '/home/john/work/python/john/prga/examples/target/bcd2bin/tiny_k4_N2_8x8' make: [../Makefile.in:27: all] Error 2

angl-dev commented 4 years ago

Hi @naeimiali7 !

I see you didn't use PRGA's virtual environment, and based on the VTR version you also installed your own VTR (so I'd assume you did the same for Yosys). This is causing a tool version mismatch.

I'd suggest you either use PRGA's virtual environment (if your envscr/install finished successfully, you should get VTR and Yosys in the PRGA directory, and after envscr/activate the VTR/Yosys binary from the PRGA directory will be chosen), or go to your VTR/Yosys directory, check out the commits as used in PRGA and recompile.

These open-source tools are evolving really fast and not always back-compatible. Therefore you should use the exact commit as listed in this repo.