Closed naeimiali7 closed 3 years ago
Hi @naeimiali7 !
I see you didn't use PRGA's virtual environment, and based on the VTR version you also installed your own VTR (so I'd assume you did the same for Yosys). This is causing a tool version mismatch.
I'd suggest you either use PRGA's virtual environment (if your envscr/install
finished successfully, you should get VTR and Yosys in the PRGA directory, and after envscr/activate
the VTR/Yosys binary from the PRGA directory will be chosen), or go to your VTR/Yosys directory, check out the commits as used in PRGA and recompile.
These open-source tools are evolving really fast and not always back-compatible. Therefore you should use the exact commit as listed in this repo.
Thanks for your reply @leon575777642 , yes, like you said the problem was version. I got them from master branch :)
I got your source code from here and install all modules "YOYS, VTR, PRGA" without any error, and done all the process which indicated in the documentation.
then I built an FPGA "tiny/k4/N2_8x8" without any error, but during implementation and simulation I got the following error :
Could anyone help me solve this issue?
Thanks in advance.
Output of make :
University of Toronto verilogtorouting.org vtr-users@googlegroups.com This is free open source code under MIT license.
VPR was run with the following command-line: vpr /home/john/work/python/john/prga/examples/fpga/tiny/k4_N2_8x8/vpr/arch.xml bcd2bin.blif --circuit_format eblif --pack --net_file bcd2bin.net --constant_net_method route
Architecture file: /home/john/work/python/john/prga/examples/fpga/tiny/k4_N2_8x8/vpr/arch.xml Circuit name: bcd2bin
Loading Architecture Description
Loading Architecture Description took 0.00 seconds (max_rss 14.2 MiB, delta_rss +0.0 MiB)
Building complex block graph
Building complex block graph took 0.00 seconds (max_rss 14.2 MiB, delta_rss +0.0 MiB)
Error 1: Type: Blif file File: bcd2bin.blif Line: 158 Message: Failed to find matching architecture model for '$_SDFFPP0'
Load circuit
Found constant-zero generator '$false' Found constant-one generator '$true' Found constant-zero generator '$undef'
Load circuit took 0.00 seconds (max_rss 16.1 MiB, delta_rss +1.9 MiB)
The entire flow of VPR took 0.00 seconds (max_rss 16.1 MiB) make[1]: [Makefile.sim:201: bcd2bin.net] Error 1 make[1]: Leaving directory '/home/john/work/python/john/prga/examples/target/bcd2bin/tiny_k4_N2_8x8' make: [../Makefile.in:27: all] Error 2