Add an option to generate SystemVerilog files

PrincetonUniversity / prga

Open-source FPGA research and prototyping framework.

http://parallel.princeton.edu/prga/

BSD 3-Clause "New" or "Revised" License

192 stars 24 forks source link

Closed angl-dev closed 3 years ago

angl-dev commented 3 years ago

SystemVerilog offers many great features that simplify/clarify code, and more importantly, enhance testability (assertions, etc.)