angl-dev
commented
1 month ago @minsikky you are correct about the timing loops. Unfortunately these loops are essential to the conventional FPGA architecture. We explained and proposed solutions to the problem here: https://ieeexplore.ieee.org/document/9221519 .
I cannot provide example scripts, firstly because it's difficult to remove all proprietary information from the script while keeping the script relevant, secondly because the FPGA architectures might be largely different. At a high level, I suggest synthesizing the CLBs first, creating timing models for the CLBs with all combinational feedthrough paths removed from the timing models, them synthesizing at the array level using the timing models. This is explained in the paper above.
I'm happy to offer more help via a zoom call.
Hello,
I'm trying to run synthesis for the generated FPGA RTL using Synopsys DC Compiler. However, the tool is detecting millions of timing loops and it won't be able to finish synthesis. I suspect that these timing loops are caused by the combinatorial connections of the CLBs through switches.
Could you please provide some example synthesis flows or constraint scripts to properly synthesize the RTL? Detailed examples would be greatly appreciated.