Closed buddynohair closed 3 years ago
Hi @buddynohair sorry for the late reply. If you run make
inside any design under example/target/*/*
successfully, there should be an output file named {design}.memh
. This is the bitstream in Verilog memory dump format.
Issue merged with #11
Hello, may i ask, if there is a way that i can get the bitstream file after running the design?