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PrincetonUniversity / prga

Open-source FPGA research and prototyping framework.
http://parallel.princeton.edu/prga/
BSD 3-Clause "New" or "Revised" License
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bitstream generation #8

Closed buddynohair closed 3 years ago

buddynohair commented 4 years ago

Hello, may i ask, if there is a way that i can get the bitstream file after running the design?

angl-dev commented 4 years ago

Hi @buddynohair sorry for the late reply. If you run make inside any design under example/target/*/* successfully, there should be an output file named {design}.memh. This is the bitstream in Verilog memory dump format.

angl-dev commented 3 years ago

Issue merged with #11